Abstract: A glitch absorbing buffer reduces glitch power in digital circuits. The glitch absorbing buffer includes a logic element configured to identify a digital logic glitch and a delay circuit configured to selectively delay one input to a logic element. The amount of delay imposed is equivalent to a pulse width of the glitch. A Schmitt trigger may amplify the low pass behavior on the input.

Abstract: A time difference amplifier (TDA) including a first delay storage unit (DSU) configured to generate a first output signal including a first transition in response to a first transition of a first input signal and a first transition of a first read signal, and a second DSU configured to generate a second output signal including a second transition in response to a second transition of a second input signal and a second transition of a second read signal. A first delay between the first and second transitions of the first and second output signals is based on a second delay between the first and second transitions of the first and second input signals and a third delay between the first and second transitions in the first and second read signals. First and second delay elements generate the first and second read signals by delaying the first and second input signals.