Abstract: A computer implemented method for a multi-layer integrated circuit routing tool connecting sources with nets to sinks in a hierarchical multi-layer integrated circuit design environment, the method including creating a cycle reach table containing a first set of information parameters for two dimensional nets per metal layer combination, creating a repeater reach table containing a second set of information parameters per constraint class, preparing a working list of nets, preparing a list of blocks larger than repeater reach dimensions, connecting a source pin to a sink pin on preassigned metal layers, by routing the net based on the given constraint class.

Abstract: A semiconductor circuit design method, system and computer program product for placing a unit pin on a boundary of a unit of a semiconductor circuit to be designed may be provided. Pin position data is received, wherein the pin position data comprises a chip pin position of a chip pin within the chip area and outside of the unit of a semiconductor circuit, to which the unit pin is to be electrically connected. The coordinates of a center point of the unit are determined, as well as a line crossing the center point and the chip pin position. The unit pin is placed on an intersection of the boundary of the unit and the line crossing the center point.

Abstract: A semiconductor circuit design method, system and computer program product for placing a unit pin on a boundary of a unit of a semiconductor circuit to be designed may be provided. Pin position data is received, wherein the pin position data comprises a chip pin position of a chip pin within the chip area and outside of the unit of a semiconductor circuit, to which the unit pin is to be electrically connected. The coordinates of a center point of the unit are determined, as well as a line crossing the center point and the chip pin position. The unit pin is placed on an intersection of the boundary of the unit and the line crossing the center point.

Abstract: A semiconductor circuit design method, system and computer program product for placing a unit pin on a boundary of a unit of a semiconductor circuit to be designed may be provided. Pin position data is received, wherein the pin position data comprises a chip pin position of a chip pin within the chip area and outside of the unit of a semiconductor circuit, to which the unit pin is to be electrically connected. The coordinates of a center point of the unit are determined, as well as a line crossing the center point and the chip pin position. The unit pin is placed on an intersection of the boundary of the unit and the line crossing the center point.

Abstract: Systems and methods to perform integrated circuit development include identifying one or more multi-sink nets in a design of the integrated circuit. Each of the one or more multi-sink nets includes a source that supplies signals to two or more sinks. A method includes determining a wire tag for each of the two or more sinks of each of the one or more multi-sink nets. Each wire tag defines characteristics of a wire connecting the source to the sink, and the characteristics include a wire width and a range of metal layers within the integrated circuit for traversal of the wire. The method also includes providing the design and the wire tags for fabrication of the integrated circuit.

Abstract: Systems and methods to perform integrated circuit development include identifying one or more multi-sink nets in a design of the integrated circuit. Each of the one or more multi-sink nets includes a source that supplies signals to two or more sinks. A method includes determining a wire tag for each of the two or more sinks of each of the one or more multi-sink nets. Each wire tag defines characteristics of a wire connecting the source to the sink, and the characteristics include a wire width and a range of metal layers within the integrated circuit for traversal of the wire. The method also includes providing the design and the wire tags for fabrication of the integrated circuit.

Abstract: Managing feedthrough wiring for an integrated circuit via design data is provided. The integrated circuit includes a sub-unit, which further includes a feedthrough wire that forwards a digital signal from an input of the sub-unit to an output of the sub-unit. The design data describes the feedthrough wiring of the sub-unit. Management of the feedthrough wiring includes determining physical constraint data from parameter data of the feedthrough wire and timing constraint data related to the feedthrough wire from the physical constraint data. The design data is then synthesized based on the timing constraint data.

Abstract: A method for processing design data for a semiconductor circuit may be provided. The design data describe a signal line and related physical characteristics. The method comprises receiving the design data for the signal line, receiving constraint data describing a blockage area, and determining a segment of the signal line that would overlap with the blockage area assuming a direct path from the source to the sink. The method comprises further determining for the segment, based on the length of the segment, whether the segment is route-able without inserting a buffer while meeting the timing constraints, and modifying, in case a segment is not route-able without inserting a buffer, the physical characteristics of the signal line. Thereby, the determining the segment, the determining whether the segment length is route-able, and the modifying the physical characteristics is performed before placing buffers in the signal line and routing the signal line.

Abstract: Managing feedthrough wiring for an integrated circuit via design data is provided. The integrated circuit includes a sub-unit, which further includes a feedthrough wire that forwards a digital signal from an input of the sub-unit to an output of the sub-unit. The design data describes the feedthrough wiring of the sub-unit. Management of the feedthrough wiring includes determining physical constraint data from parameter data of the feedthrough wire and timing constraint data related to the feedthrough wire from the physical constraint data. The design data is then synthesized based on the timing constraint data.

Abstract: There is provided a computer implemented method for processing a formal specification of a digital circuit. The specification comprises information about a signal path for forwarding a digital signal from a source to a sink. The method comprises inputting the formal specification; identifying at least one signal group and at least one signal path belonging to the signal group based on the formal specification; inputting physical design constraints; and calculating, based on the physical design constraints and the at least one signal group, a number of clocked stages to be inserted into the signal path, such that the signal paths of a certain signal group have the same calculated number of clocked stages.

Abstract: A method for improving a routing of a single chip multi-sink net of a semiconductor circuit may be provided. The method includes receiving a netlist describing at least one routed multi-sink net and timing information related to a signal propagation delay between a source and individual sinks. The method also includes determining a timing slack value related to a routed path from the source to the individual sinks and determining at least one critical sink out of the individual sinks based on the related timing slack value, wherein the critical sink has a related timing slack value that is larger than a predefined threshold value. The method additionally includes deleting all routed wires of the multi-sink net, and rerouting the multi-sink net, wherein at least one subnet of the multi-sink net, comprising the source and the critical sink, is routed before routing the remaining individual sinks of the multi-sink net.

Abstract: Methods are provided for optimizing a routing of a signal path in terms of delay and signal integrity in a semiconductor device. The signal path includes at least one track in a metal layer. The method includes selecting an already routed original signal path to be optimized, modifying at least one original routing parameter, creating an alternative signal path based on the modified routing parameter value, determining at least one timing value describing the delay and signal integrity of the alternative signal path and signal integrity, and replacing the already routed original signal path by the alternative signal path based on the timing value indicating that the alternative signal path complies with predefined constraints related to the delay and signal integrity.

Abstract: There is provided a computer implemented method for processing a formal specification of a digital circuit. The specification comprises information about a signal path for forwarding a digital signal from a source to a sink. The method comprises inputting the formal specification; identifying at least one signal group and at least one signal path belonging to the signal group based on the formal specification; inputting physical design constraints; and calculating, based on the physical design constraints and the at least one signal group, a number of clocked stages to be inserted into the signal path, such that the signal paths of a certain signal group have the same calculated number of clocked stages.

Abstract: A method for processing design data for a semiconductor circuit may be provided. The design data describe a signal line and related physical characteristics. The method comprises receiving the design data for the signal line, receiving constraint data describing a blockage area, and determining a segment of the signal line that would overlap with the blockage area assuming a direct path from the source to the sink. The method comprises further determining for the segment, based on the length of the segment, whether the segment is route-able without inserting a buffer while meeting the timing constraints, and modifying, in case a segment is not route-able without inserting a buffer, the physical characteristics of the signal line. Thereby, the determining the segment, the determining whether the segment length is route-able, and the modifying the physical characteristics is performed before placing buffers in the signal line and routing the signal line.

Abstract: A method is provided for facilitating an integrated circuit design layout. The method includes receiving a netlist including a plurality of subnets. For each subnet, the method also includes obtaining a Steiner net length value and related net delays in a signal path for a metal wiring layer using timings of all involved circuits of the subnet, and determining whether the net delay is smaller than a predefined value. On a negative outcome of the determination, a wire delay is ascertained for the named metal wiring layer based on a maximum buffer distance retrieved from a cycle reach table, and determining whether the ascertained wire delay is below the related net delay. On a positive outcome of the second determination, a next increased metal wire width is selected and a metal wire based wire delay for the named metal wiring layer including a buffer is ascertained.

Abstract: A method is provided for facilitating an integrated circuit design layout. The method includes receiving a netlist including a plurality of subnets. For each subnet, the method also includes obtaining a Steiner net length value and related net delays in a signal path for a metal wiring layer using timings of all involved circuits of the subnet, and determining whether the net delay is smaller than a predefined value. On a negative outcome of the determination, a wire delay is ascertained for the named metal wiring layer based on a maximum buffer distance retrieved from a cycle reach table, and determining whether the ascertained wire delay is below the related net delay. On a positive outcome of the second determination, a next increased metal wire width is selected and a metal wire based wire delay for the named metal wiring layer including a buffer is ascertained.

Abstract: Methods are provided for optimizing a routing of a signal path in terms of delay and signal integrity in a semiconductor device. The signal path includes at least one track in a metal layer. The method includes selecting an already routed original signal path to be optimized, modifying at least one original routing parameter, creating an alternative signal path based on the modified routing parameter value, determining at least one timing value describing the delay and signal integrity of the alternative signal path and signal integrity, and replacing the already routed original signal path by the alternative signal path based on the timing value indicating that the alternative signal path complies with predefined constraints related to the delay and signal integrity.

Abstract: A computer-implemented method for calculating an effect on timing of moving a pin from an edge position to an inboard position in processing large block synthesis (LBS). The method includes determining first timing details at the inboard position, based on internal wire segments between a signal source and the inboard position. The method further includes selecting an upper metal layer as a virtual wire between the edge position and the inboard position. The method further includes calculating capacitance and resistance of the virtual wire. The method further includes updating driver strength of a driver between the signal source and the inboard position. The method further includes determining second timing details at the inboard position, based on wire loads of the virtual wire. The method further includes modifying an assertion of the pin at the inboard position, based on the first timing details and the second timing details.

Abstract: A computer-implemented method for calculating an effect on timing of moving a pin from an edge position to an inboard position in processing large block synthesis (LBS). The method includes determining first timing details at the inboard position, based on internal wire segments between a signal source and the inboard position. The method further includes selecting an upper metal layer as a virtual wire between the edge position and the inboard position. The method further includes calculating capacitance and resistance of the virtual wire. The method further includes updating driver strength of a driver between the signal source and the inboard position. The method further includes determining second timing details at the inboard position, based on wire loads of the virtual wire. The method further includes modifying an assertion of the pin at the inboard position, based on the first timing details and the second timing details.

Abstract: A computer-implemented method for calculating an effect on timing of moving a pin from an edge position to an inboard position in processing large block synthesis (LBS). The method includes determining first timing details at the inboard position, based on internal wire segments between a signal source and the inboard position. The method further includes selecting an upper metal layer as a virtual wire between the edge position and the inboard position. The method further includes calculating capacitance and resistance of the virtual wire. The method further includes updating driver strength of a driver between the signal source and the inboard position. The method further includes determining second timing details at the inboard position, based on wire loads of the virtual wire. The method further includes modifying an assertion of the pin at the inboard position, based on the first and the second timing details.