Patents by Inventor Lukas Kranz

Lukas Kranz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11888037
    Abstract: A power semiconductor device includes a wide-bandgap semiconductor layer having an active region and a termination region that laterally surrounds the active region. The wide-bandgap semiconductor layer has a first recess that is recessed from the first main side in the termination region and surrounds the active region and a second recess that is recessed from the first main side in the active region and is filled with an insulating material. A depth of the second recess is the same as a depth of the first recess. A field plate on the first main side of the wide-bandgap semiconductor layer exposes a first portion of the wide-bandgap semiconductor layer in the termination region.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: January 30, 2024
    Assignee: Hitachi Energy Ltd
    Inventors: Andrei Mihaila, Lars Knoll, Lukas Kranz
  • Publication number: 20230411510
    Abstract: In one embodiment, the power field-effect transistor (1) comprises: at least two source regions (21) at a top side (20) of a semiconductor body (2), a drain region (22) at a back side (23) of the semiconductor body (2), at least two charge barrier regions (24) in the semiconductor body (2) so that electrically between each one of the source regions (21) and the drain region (22) there is one of the charge barrier regions (24), and a gate electrode (3) located in a trench (4) in the semiconductor body (2), and the charge barrier regions (24) are located adjacent to the trench (4), wherein, next to the trench (4) and seen in a first plane (A) perpendicular with the top side (21) and a main elongation direction (L) of the trench (4), the top side (21) is formed only by the source regions (21).
    Type: Application
    Filed: November 4, 2020
    Publication date: December 21, 2023
    Inventors: Stephan WIRTHS, Lars KNOLL, Lukas KRANZ
  • Patent number: 11302811
    Abstract: A silicon carbide power device, e.g., a vertical power MOSFET or an IGBT, includes a silicon carbide wafer. A first stressor and a second stressor are arranged in the silicon carbide wafer at a first main side. A first channel region, a first portion of a drift layer and a second channel region are laterally arranged between the first stressor and the second stressor in a second lateral direction parallel to the first main side and perpendicular to the first lateral direction. A stress can be introduced by the first stressor and the second stressor in the first channel region and in the second channel region.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: April 12, 2022
    Assignee: Hitachi Energy Switzerland AG
    Inventors: Marco Bellini, Lars Knoll, Lukas Kranz
  • Publication number: 20220045213
    Abstract: A silicon carbide power device, e.g., a vertical power MOSFET or an IGBT, includes a silicon carbide wafer. A first stressor and a second stressor are arranged in the silicon carbide wafer at a first main side. A first channel region, a first portion of a drift layer and a second channel region are laterally arranged between the first stressor and the second stressor in a second lateral direction parallel to the first main side and perpendicular to the first lateral direction. A stress can be introduced by the first stressor and the second stressor in the first channel region and in the second channel region.
    Type: Application
    Filed: December 16, 2019
    Publication date: February 10, 2022
    Inventors: Marco Bellini, Lars Knoll, Lukas Kranz
  • Publication number: 20210020753
    Abstract: A power semiconductor device includes a wide-bandgap semiconductor layer having an active region and a termination region that laterally surrounds the active region. The wide-bandgap semiconductor layer has a first recess that is recessed from the first main side in the termination region and surrounds the active region and a second recess that is recessed from the first main side in the active region and is filled with an insulating material. A depth of the second recess is the same as a depth of the first recess. A field plate on the first main side of the wide-bandgap semiconductor layer exposes a first portion of the wide-bandgap semiconductor layer in the termination region.
    Type: Application
    Filed: March 5, 2019
    Publication date: January 21, 2021
    Inventors: Andrei Mihaila, Lars Knoll, Lukas Kranz
  • Publication number: 20150136220
    Abstract: Conventionally, CdTe solar cells are grown in superstrate configuration where the light enters the photovoltaic device through a transparent substrate. Still, efficiencies of CdTe solar cells grown in substrate configuration have so far been considerably lower than those grown in superstrate configuration. This invention discloses a photovoltaic device (0) in substrate configuration and a process of making thereof with which efficiencies approaching those of superstrate devices can be reproducibly achieved. Furthermore, long term stability is expected to be better than in state of the art devices. This method is advantageous because the growth in substrate configuration offers several advantages like the growth on metal foils and a more precise control of the junction.
    Type: Application
    Filed: May 31, 2013
    Publication date: May 21, 2015
    Applicant: EMPA EIDG. MATERIALPRÜFUNGS-UND FORSCHUNGSANSTALT
    Inventors: Lukas Kranz, Christina Gretener, Julian Perrenoud, Stephan Buecheler, Ayodhya N. Tiwari