Abstract: A host read request affects a request address range of a main storage. A speculative address range proximate to the request address range is defined. Speculative data stored in the speculative address range is not requested via the host read request. A criterion is determined that is indicative of future read requests of associated with the speculative data. The speculative data is copied from the main storage to at least one of a non-volatile cache and a volatile cache together with data of the host read request in response to the criterion meeting a threshold. The non-volatile cache and the volatile cache mirror respective portions of the main storage.

Abstract: Data stripes and addressing for flash memory devices are provided. Flash memory devices illustratively have a plurality of programmable devices that are capable of simultaneously storing data. A plurality of erasure blocks are within each of the programmable devices, and each erasure block has pages of transistors. The flash memory devices are logically organized as a plurality of stripes. Each stripe has a height and a width. In an embodiment, the stripe height is greater than one page. In another embodiment, the stripe width is less than all of the programmable devices within the flash memory device.

Abstract: The present disclosure provides a data storage system. In one example, the data storage system includes a data storage media component having a plurality of data storage locations. A first set of the plurality of data storage locations are allocated for a main data storage area. The data storage system also includes a controller configured to define a write cache for the main data storage area by selectively allocating a second set of the plurality of data storage locations.

Abstract: The present disclosure provides a data storage system. In one example, the data storage system includes a data storage media component having a plurality of data storage locations. A first set of the plurality of data storage locations are allocated for a main data storage area. The data storage system also includes a controller configured to define a write cache for the main data storage area by selectively allocating a second set of the plurality of data storage locations.

Abstract: Data stripes and addressing for flash memory devices are provided. Flash memory devices illustratively have a plurality of programmable devices that are capable of simultaneously storing data. A plurality of erasure blocks are within each of the programmable devices, and each erasure block has pages of transistors. The flash memory devices are logically organized as a plurality of stripes. Each stripe has a height and a width. In an embodiment, the stripe height is greater than one page. In another embodiment, the stripe width is less than all of the programmable devices within the flash memory device.