Abstract: An optical component driving mechanism is provided. The optical component driving mechanism includes a first movable portion, a fixed portion, and a first driving assembly. The fixed portion includes a first opening. The first movable portion is movable relative to the fixed portion. The first driving assembly is configured to drive the first movable portion to move relative to the fixed portion.

Abstract: A method includes providing a first channel layer and a second channel layer over a substrate; forming a first patterned hard mask covering the first channel layer and exposing the second channel layer; selectively depositing a cladding layer on the second channel layer and not on the first patterned hard mask; performing a first thermal drive-in process; removing the first patterned hard mask; after removing the first patterned hard mask, forming an interfacial dielectric layer on the cladding layer and the first channel layer; and forming a high-k dielectric layer on the interfacial dielectric layer.

Abstract: A semiconductor device includes a substrate, a first semiconductor fin and a second semiconductor fin protruding from the substrate, an isolation feature disposed on the substrate and on sidewalls of the first and second semiconductor fins, a gate structure disposed on the isolation feature. The semiconductor device also includes a dielectric fin disposed on the isolation feature and sandwiched between the first and second semiconductor fins. A middle portion of the dielectric fin separates the gate structure into a first gate structure segment engaging the first semiconductor fin and a second gate structure segment engaging the second semiconductor fin.

Abstract: Semiconductor structures and the manufacturing method thereof are disclosed. An exemplary semiconductor structure according to the present disclosure includes a first base portion and a second base portion, an isolation feature sandwiched between the first base portion and the second base portion, a center dielectric fin over the isolation feature, a first anti-punch-through (APT) feature over the first base portion, a second APT feature over the second base portion, a first stack of channel members over the first APT feature, and a second stack of channel members over the second APT feature. The center dielectric fin is sandwiched between the first stack of channel members and the second stack of channel members as well as between the first APT feature and the second APT feature.

Abstract: A transmission structure of a hub motor has a hub shell, an axle, a motor unit, and a clutch assembly. The clutch assembly connects with the hub shell and the motor unit, and includes a driving ring, an output disc, a fixing base, a clutch disc, and a pressing ring. The motor unit drives the driving ring to rotate. The output disc is capable of driving the hub shell to rotate. The driving ring drives the clutch disc to rotate and further drives the pressing ring; the pressing ring then pushes the clutch disc to contact the output disc and further drives the output disc to rotate. The fixing base is magnetic and is disposed between the output disc and the motor unit. The clutch disc is magnetically attractable such that the clutch disc separates from the output disc when the motor unit stops working to prevent the motor unit from providing resistance.

Abstract: A segmented capacitance calibration circuit applied in a pure capacitor array structure includes a first calibration unit, a second calibration unit and a selection switch which are all connected with a scaling capacitor. The first and second calibration units include at least one capacitor, and the selection switch is configured to select the first or second calibration unit to be connected to the pure capacitor array structure. When the first calibration unit is connected to the pure capacitor array structure and in parallel with the scaling capacitor, a negative error calibration is performed on the scaling capacitor. When the second calibration unit is connected to the pure capacitor array structure and in series with the scaling capacitor, a positive error calibration is performed on the scaling capacitor. The nonlinear problem caused by the precision error of the scaling capacitor in the pure capacitor array structure is solved.

Abstract: An illumination system that provides an illumination beam is provided. The illumination system includes a first light source module, a second light source module, a third light source module, a first optical element, a second optical element, and a third optical element. The first light source module and the second light source module provide a first color light beam, a second color light beam, and a third color light beam. The third light source module provides a third color light beam. The first optical element, the second optical element and the third optical element are disposed on transmission paths of the first color light beam, the second color light beam and the third color light beam, and the first light source module and the second light source module are respectively located on opposite sides of the first optical element and the second optical element.

Abstract: A semiconductor structure includes a stack of semiconductor layers disposed over a substrate, a metal gate stack having a top portion disposed over the stack of semiconductor layers and a bottom portion interleaved with the stack of semiconductor layers, an inner spacer disposed on sidewalls of the bottom portion of the metal gate stack, an air gap enclosed in the inner spacer, and an epitaxial source/drain (S/D) feature disposed over the inner spacer and adjacent to the metal gate stack.

Abstract: A method for making a semiconductor device includes forming a ROX layer on a substrate and a patterned silicon oxynitride layer on the patterned ROX layer; conformally forming a dielectric oxide layer to cover the substrate, the patterned silicon oxynitride layer, and the patterned ROX layer; and fully oxidizing the patterned silicon oxynitride layer to form a fully oxidized gate oxide layer on the substrate.

Abstract: A vehicle control device and a method thereof are provided. A master processor and a slave processor simultaneously receive, monitor or process signals of a vehicle, a power management module monitors the master processor via a first watchdog signal, and the master processor monitors the slave processor via a second watchdog signal. When the power management module sends the first watchdog signal to the master processor and no response message is received, the power management module sends a first reset signal to reset the master processor, and when the master processor sends the second watchdog signal to the slave processor and no response message is received, the master processor sends a second reset signal to reset the slave processor. When the master processor and the slave processor are abnormal, a forced wake-up module outputs a high level signal to forcibly wake up the master processor and the slave processor.

Abstract: Embodiments of the present disclosure provide a method of forming sidewall spacers by filling a trench between a hybrid fin and a semiconductor fin structure. The sidewall spacer includes two fin sidewall spacer portions connected by a gate sidewall spacer portion. The fin sidewall spacer portion has a substantially uniform profile to provide uniform protection for vertically stacked channel layers and eliminate any gaps and leaks between inner spacers and sidewall spacers.

Abstract: A semiconductor device structure, along with methods of forming such, are described. The method includes forming a first dielectric feature between first and the second fin structures, wherein each first and second fin structure includes first semiconductor layers and second semiconductor layers alternatingly stacked and in contact with the first dielectric layer. The method also includes removing the second semiconductor layers so that the first semiconductor layers of the first and second fin structures extend laterally from a first side and a second side of the first dielectric feature, respectively, trimming the first dielectric feature so that the first dielectric feature has a reduced thickness on both first and the second sides, and forming a gate electrode layer to surround each of the first semiconductor layers of the first and second fin structures.

Abstract: Methods and devices that include a multigate device having a channel layer disposed between a source feature and a drain feature, a metal gate that surrounds the channel layer, and a first air gap spacer interposing the metal gate and the source feature and a second air gap spacer interposing the metal gate and the drain feature. A backside contact extends to the source feature. A power line metallization layer is connected to the backside contact.

Abstract: A semiconductor device includes channel members vertically stacked, a gate structure wrapping around the channel members, a gate spacer disposed on sidewalls of the gate structure, an epitaxial feature abutting the channel members, and an inner spacer layer interposing the gate structure and the epitaxial feature. In a top view of the semiconductor device, the inner spacer layer has side portions in physical contact with the gate spacer and a middle portion stacked between the side portions. In a lengthwise direction of the channel members, the middle portion of the inner spacer layer is thicker than the side portions of the inner spacer layer.

Abstract: An integrated circuit is provided and includes a multi-bit cell having multiple bit cells disposed in multiple cell rows. The bit cells include M bit cells, M being positive integers. A first bit cell of the bit cells and a M-th bit cell of the bit cells are arranged diagonally in different cell rows in the multi-bit cell. The multi-bit cell includes first to fourth cell boundaries. The first and second boundaries extend in a first direction and the third and fourth boundaries extend in a second direction different from the first direction. The first bit cell and a second bit cell of the bit cells abut the third cell boundary, and the first bit cell and a (M/2+1)-th bit cell of the bit cells abut the first cell boundary.

Abstract: The present disclosure relates to a hybrid integrated circuit. In one implementation, an integrated circuit may have a first region with a first gate structure having a ferroelectric gate dielectric, at least one source associated with the first gate of the first region, and at least one drain associated with the first gate structure of the first region. Moreover, the integrated circuit may have a second region with a second gate structure having a high-? gate dielectric, at least one source associated with the second gate structure of the second region, and at least one drain associated with the second gate structure of the second region. The integrated circuit may further have at least one trench isolation between the first region and the second region.

Abstract: An optical system is provided. The optical system is used for disposing on an electronic device. The optical system includes a movable portion, a fixed portion, a first driving assembly, and a support module. The movable portion is used for connecting to an optical module. The fixed portion is affixed on the electronic device, and the movable portion is movable relative to the fixed portion. The first driving assembly is used for driving the movable portion to move relative to the fixed portion. The movable portion is movably connected to the fixed portion through the support module.

Abstract: A method for processing an integrated circuit includes forming first and second gate all around transistors. The method forms a dipole oxide in the first gate all around transistor without forming the dipole oxide in the second gate all around transistor. This is accomplished by entirely removing an interfacial dielectric layer and a dipole-inducing layer from semiconductor nanosheets of the second gate all around transistor before redepositing the interfacial dielectric layer on the semiconductor nanosheets of the second gate all around transistor.

Abstract: A method of power management includes steps of: in response to receiving from a server host a sleep command, an expander first outputting a predetermined register value to a processing unit in a normal state, and then switching to a power-saving state and outputting an interrupt signal to the processing unit; the processing unit determining whether both the predetermined register value and the interrupt signal are received; and when it is determined that both the predetermined register value and the interrupt signal have been received, the processing unit controlling a power supply to output standby electricity, making the expander and the processing unit operate based on the standby electricity.

Abstract: A first fin structure is disposed over a substrate. The first fin structure contains a semiconductor material. A gate dielectric layer is disposed over upper and side surfaces of the first fin structure. A gate electrode layer is formed over the gate dielectric layer. A second fin structure is disposed over the substrate. The second fin structure is physically separated from the first fin structure and contains a ferroelectric material. The second fin structure is electrically coupled to the gate electrode layer.