Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a chip structure including a substrate and a wiring structure over a first surface of the substrate. The semiconductor device structure includes a first seed layer over the wiring structure, a first inner wall of the first enlarged portion, and a second inner wall of the neck portion. The semiconductor device structure includes a second seed layer over a second surface of the substrate, a third inner wall of the second enlarged portion, and the first seed layer over the second inner wall of the neck portion. The second seed layer is in direct contact with the first seed layer.

Abstract: A semiconductor package includes a die having a plurality of devices over a first substrate, where the first substrate includes a dopant at a first concentration and the first substrate has a first width along a horizontal direction. The semiconductor package further includes a second substrate fused with the first substrate, where the second substrate includes the dopant at a second concentration greater than the first concentration.

Abstract: A method includes forming a first package component, which formation process includes forming a first plurality of openings in a first dielectric layer, depositing a first metallic material into the first plurality of openings, performing a planarization process on the first metallic material and the first dielectric layer to form a plurality of metal pads in the first dielectric layer, and selectively depositing a second metallic material on the plurality of metal pads to form a plurality of bond pads. The first plurality of bond pads comprise the plurality of metal pads and corresponding parts of the second metallic material. The first package component is bonded to a second package component.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a chip structure including a substrate and a wiring structure over a first surface of the substrate. The method includes removing a first portion of the wiring structure adjacent to the hole to widen a second portion of the hole in the wiring structure. The second portion has a first width increasing in a first direction away from the substrate. The method includes forming a first seed layer over the wiring structure and in the hole. The method includes thinning the substrate from a second surface of the substrate until the first seed layer in the hole is exposed. The method includes forming a second seed layer over the second surface of the substrate and the first seed layer in the hole.

Abstract: A method includes forming a first package component, which formation process includes forming a first plurality of openings in a first dielectric layer, depositing a first metallic material into the first plurality of openings, performing a planarization process on the first metallic material and the first dielectric layer to form a plurality of metal pads in the first dielectric layer, and selectively depositing a second metallic material on the plurality of metal pads to form a plurality of bond pads. The first plurality of bond pads comprise the plurality of metal pads and corresponding parts of the second metallic material. The first package component is bonded to a second package component.

Abstract: A method includes bonding a supporting substrate to a semiconductor substrate of a wafer. A bonding layer is between, and is bonded to both of, the supporting substrate and the semiconductor substrate. A first etching process is performed to etch the supporting substrate and to form an opening, which penetrates through the supporting substrate and stops on the bonding layer. The opening has substantially straight edges. The bonding layer is then etched. A second etching process is performed to extend the opening down into the semiconductor substrate. A bottom portion of the opening is curved.

Abstract: A method includes forming a first package component, which formation process includes forming a first plurality of openings in a first dielectric layer, depositing a first metallic material into the first plurality of openings, performing a planarization process on the first metallic material and the first dielectric layer to form a plurality of metal pads in the first dielectric layer, and selectively depositing a second metallic material on the plurality of metal pads to form a plurality of bond pads. The first plurality of bond pads comprise the plurality of metal pads and corresponding parts of the second metallic material. The first package component is bonded to a second package component.

Abstract: A method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is plated on the second conductive feature. The method further includes removing the patterned photo resist, and etching the metal seed layer.

Abstract: A method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is plated on the second conductive feature. The method further includes removing the patterned photo resist, and etching the metal seed layer.

Abstract: A method for forming a semiconductor device structure is provided. The method includes providing a chip structure including a substrate and a wiring structure over a first surface of the substrate. The method includes removing a first portion of the wiring structure adjacent to the hole to widen a second portion of the hole in the wiring structure. The second portion has a first width increasing in a first direction away from the substrate. The method includes forming a first seed layer over the wiring structure and in the hole. The method includes thinning the substrate from a second surface of the substrate until the first seed layer in the hole is exposed. The method includes forming a second seed layer over the second surface of the substrate and the first seed layer in the hole.

Abstract: A method includes forming a first package component, which formation process includes forming a first plurality of openings in a first dielectric layer, depositing a first metallic material into the first plurality of openings, performing a planarization process on the first metallic material and the first dielectric layer to form a plurality of metal pads in the first dielectric layer, and selectively depositing a second metallic material on the plurality of metal pads to form a plurality of bond pads. The first plurality of bond pads comprise the plurality of metal pads and corresponding parts of the second metallic material. The first package component is bonded to a second package component.

Abstract: A method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is plated on the second conductive feature. The method further includes removing the patterned photo resist, and etching the metal seed layer.

Abstract: A method includes bonding a supporting substrate to a semiconductor substrate of a wafer. A bonding layer is between, and is bonded to both of, the supporting substrate and the semiconductor substrate. A first etching process is performed to etch the supporting substrate and to form an opening, which penetrates through the supporting substrate and stops on the bonding layer. The opening has substantially straight edges. The bonding layer is then etched. A second etching process is performed to extend the opening down into the semiconductor substrate. A bottom portion of the opening is curved.

Abstract: A method includes forming a first package component, which formation process includes forming a first plurality of openings in a first dielectric layer, depositing a first metallic material into the first plurality of openings, performing a planarization process on the first metallic material and the first dielectric layer to form a plurality of metal pads in the first dielectric layer, and selectively depositing a second metallic material on the plurality of metal pads to form a plurality of bond pads. The first plurality of bond pads comprise the plurality of metal pads and corresponding parts of the second metallic material. The first package component is bonded to a second package component.

Abstract: A method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is plated on the second conductive feature. The method further includes removing the patterned photo resist, and etching the metal seed layer.

Abstract: A method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is plated on the second conductive feature. The method further includes removing the patterned photo resist, and etching the metal seed layer.

Abstract: Generally, this disclosure provides examples relating to tuning etch rates of dielectric material. In an embodiment, a dielectric material is conformally deposited in first and second trenches in a substrate. Merged lateral growth fronts of the first dielectric material in the first trench form a seam in the first trench. The dielectric material is treated. The treating causes a species to be on first and second upper surfaces of the dielectric material in the first and second trenches, respectively, to be in the seam, and to diffuse into the respective dielectric material in the first and second trenches. After the treating, the respective dielectric material is etched. A ratio of an etch rate of the dielectric material in the second trench to an etch rate of the dielectric material in the first trench is altered by presence of the species in the dielectric material during the etching.

Abstract: Generally, this disclosure provides examples relating to tuning etch rates of dielectric material. In an embodiment, a dielectric material is conformally deposited in first and second trenches in a substrate. Merged lateral growth fronts of the first dielectric material in the first trench form a seam in the first trench. The dielectric material is treated. The treating causes a species to be on first and second upper surfaces of the dielectric material in the first and second trenches, respectively, to be in the seam, and to diffuse into the respective dielectric material in the first and second trenches. After the treating, the respective dielectric material is etched. A ratio of an etch rate of the dielectric material in the second trench to an etch rate of the dielectric material in the first trench is altered by presence of the species in the dielectric material during the etching.

Abstract: An electronic device including a bio-polymer material and a method for manufacturing the same are disclosed. The electronic device of the present invention comprises: a substrate; a first electrode disposed on the substrate; a bio-polymer layer disposed on the first electrode, wherein the bio-polymeric material is selected from a group consisting of wool keratin, collagen hydrolysate, gelatin, whey protein and hydroxypropyl methylcellulose; and a second electrode disposed on the biopolymer material layer. The present invention is suitable for various electronic devices such as an organic thin film transistor, an organic floating gate memory, or a metal-insulator-metal capacitor.

Abstract: A circuit board and a method for manufacturing the same are disclosed. The circuit board of the present invention comprises: a carrier board, wherein a first circuit layer is disposed on at least one surface of the carrier board, and the first circuit layer comprises plural conductive pads; a protein dielectric layer disposed on the surface of the carrier board and the first circuit layer, wherein the protein dielectric layer has plural openings to expose the conductive pads; and a second circuit layer disposed on a surface of the protein dielectric layer, wherein the second circuit layer comprises plural first conductive vias, and each first conductive via is correspondingly formed in the opening and electrically connects to the conductive pad.