Patents by Inventor Lutz Steinbeck

Lutz Steinbeck has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • ESD-protection device and MOS-transistor having at least one integrated ESD-protection device
    Patent number: 11469222
    Abstract: Protection against electrostatic discharges is to be improved for electronic devices, or is to be provided in the first place. The device for protection against electrostatic discharges having an integrated semiconductor protection device comprises an inner region (1) configured at least as a thyristor (SCR) and at least one outer region (2a, 2b) configured as a corner region, which is formed and configured at least as a PNP transistor. The inner region (1) and the at least one outer region (2a, 2b) are arranged adjacent to one another.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: October 11, 2022
    Assignee: X-FAB Semiconductor Foundries GmbH
    Inventor: Lutz Steinbeck
  • ESD-protection device and MOS-Transistor having at least one integrated ESD-protection device
    Publication number: 20200388607
    Abstract: Protection against electrostatic discharges is to be improved for electronic devices, or is to be provided in the first place. The device for protection against electrostatic discharges having an integrated semiconductor protection device comprises an inner region (1) configured at least as a thyristor (SCR) and at least one outer region (2a, 2b) configured as a corner region, which is formed and configured at least as a PNP transistor. The inner region (1) and the at least one outer region (2a, 2b) are arranged adjacent to one another.
    Type: Application
    Filed: March 30, 2020
    Publication date: December 10, 2020
    Inventor: Lutz STEINBECK
  • LDMOS transistors for CMOS technologies and an associated production method
    Patent number: 10388785
    Abstract: In a semiconductor component or device, a lateral power effect transistor is produced as an LDMOS transistor in such a way that, in combination with a trench isolation region (12) and the heavily doped feed guiding region (28, 28A), an improved potential profile is achieved in the drain drift region (8) of the transistor. For this purpose, in advantageous embodiments, it is possible to use standard implantation processes of CMOS technology, without additional method steps being required.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: August 20, 2019
    Assignee: X-FAB SEMICONDUCTOR FOUNDRIES AG
    Inventors: Thomas Uhlig, Lutz Steinbeck
  • LDMOS TRANSISTORS FOR CMOS TECHNOLOGIES AND AN ASSOCIATED PRODUCTION METHOD
    Publication number: 20180166567
    Abstract: In a semiconductor component or device, a lateral power effect transistor is produced as an LDMOS transistor in such a way that, in combination with a trench isolation region (12) and the heavily doped feed guiding region (28, 28A), an improved potential profile is achieved in the drain drift region (8) of the transistor. For this purpose, in advantageous embodiments, it is possible to use standard implantation processes of CMOS technology, without additional method steps being required.
    Type: Application
    Filed: October 31, 2017
    Publication date: June 14, 2018
    Inventors: Thomas UHLIG, Lutz STEINBECK
  • LDMOS TRANSISTORS FOR CMOS TECHNOLOGIES AND AN ASSOCIATED PRODUCTION METHOD
    Publication number: 20160126350
    Abstract: In a semiconductor component or device, a lateral power effect transistor is produced as an LDMOS transistor in such a way that, in combination with a trench isolation region (12) and the heavily doped feed guiding region (28, 28A), an improved potential profile is achieved in the drain drift region (8) of the transistor. For this purpose, in advantageous embodiments, it is possible to use standard implantation processes of CMOS technology, without additional method steps being required.
    Type: Application
    Filed: December 16, 2015
    Publication date: May 5, 2016
    Inventors: Thomas UHLIG, Lutz Steinbeck
  • LDMOS transistors for CMOS technologies and an associated production method
    Patent number: 9224856
    Abstract: In a semiconductor component or device, a lateral power effect transistor is produced as an LDMOS transistor in such a way that, in combination with a trench isolation region (12) and the heavily doped feed guiding region (28, 28A), an improved potential profile is achieved in the drain drift region (8) of the transistor. For this purpose, in advantageous embodiments, it is possible to use standard implantation processes of CMOS technology, without additional method steps being required.
    Type: Grant
    Filed: April 7, 2011
    Date of Patent: December 29, 2015
    Assignee: X-FAB SEMICONDUCTOR FOUNDRIES AG
    Inventors: Thomas Uhlig, Lutz Steinbeck
  • LDMOS Transistors For CMOS Technologies And An Associated Production Method
    Publication number: 20130175615
    Abstract: In a semiconductor component or device, a lateral power effect transistor is produced as an LDMOS transistor in such a way that, in combination with a trench isolation region (12) and the heavily doped feed guiding region (28, 28A), an improved potential profile is achieved in the drain drift region (8) of the transistor. For this purpose, in advantageous embodiments, it is possible to use standard implantation processes of CMOS technology, without additional method steps being required.
    Type: Application
    Filed: April 7, 2011
    Publication date: July 11, 2013
    Applicant: X-Fab Semiconductor Foundries AG
    Inventors: Thomas Uhlig, Lutz Steinbeck