Patents by Inventor Lydia Wong

Lydia Wong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Electronically controlled padlock
    Patent number: 11391067
    Abstract: This invention relates to a padlock assembly 1 including a body 2 with a hand engageable portion 4 that is external to the body 2 forming part of an actuator mechanism 5. The actuator mechanism 5 is electrically controllable to adjust between an operable condition and an inoperable condition to adjust a condition of a lock mechanism 31.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: July 19, 2022
    Assignee: ASSA ABLOY AUSTRALIA PTY LIMITED
    Inventors: Brendan George, Lydia Wong
  • ELECTRONICALLY CONTROLLED PADLOCK
    Publication number: 20200165841
    Abstract: This invention relates to a padlock assembly 1 including a body 2 with a hand engageable portion 4 that is external to the body 2 forming part of an actuator mechanism 5. The actuator mechanism 5 is electrically controllable to adjust between an operable condition and an inoperable condition to adjust a condition of a lock mechanism 31.
    Type: Application
    Filed: April 5, 2018
    Publication date: May 28, 2020
    Inventors: Brendan George, Lydia Wong
  • Method of fabricating a nitrogenated silicon oxide layer and MOS device having same
    Patent number: 7928020
    Abstract: A method for fabricating a nitrogen-containing dielectric layer and semiconductor device including the dielectric layer in which a silicon oxide layer is formed on a substrate, such that an interface region resides adjacent to substrate and a surface region resides opposite the interface region. Nitrogen is introduced into the silicon oxide layer by applying a nitrogen plasma. After applying nitrogen plasma, the silicon oxide layer is annealed. The processes of introducing nitrogen into the silicon oxide layer and annealing the silicon oxide layer are repeated to create a bi-modal nitrogen concentration profile in the silicon oxide layer. In the silicon oxide layer, the peak nitrogen concentrations are situated away from the interface region and at least one of the peak nitrogen concentrations is situated in proximity to the surface region. A method for fabricating a semiconductor device is incorporating the nitrogen-containing silicon oxide layers also disclosed.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: April 19, 2011
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Jinping Liu, Ben Ong, Zhengquan Zhang, Jae Gon Lee, Lydia Wong, Bin Yang, K. H. Alex See, Meisheng Zhou, Liang Choo Hsia
  • METHOD OF FABRICATING A NITROGENATED SILICON OXIDE LAYER AND MOS DEVICE HAVING SAME
    Publication number: 20090088002
    Abstract: A method for fabricating a nitrogen-containing dielectric layer and semiconductor device including the dielectric layer in which a silicon oxide layer is formed on a substrate, such that an interface region resides adjacent to substrate and a surface region resides opposite the interface region. Nitrogen is introduced into the silicon oxide layer by applying a nitrogen plasma. After applying nitrogen plasma, the silicon oxide layer is annealed. The processes of introducing nitrogen into the silicon oxide layer and annealing the silicon oxide layer are repeated to create a bi-modal nitrogen concentration profile in the silicon oxide layer. In the silicon oxide layer, the peak nitrogen concentrations are situated away from the interface region and at least one of the peak nitrogen concentrations is situated in proximity to the surface region. A method for fabricating a semiconductor device is incorporating the nitrogen-containing silicon oxide layers also disclosed.
    Type: Application
    Filed: September 27, 2007
    Publication date: April 2, 2009
    Inventors: Jinping Liu, Ben Ong, Zhengquan Zhang, Jae Gon Lee, Lydia Wong, Bin Yang, K. H. See, Meisheng Zhou, Liang Choo Hsia
  • Method of manufacturing a semiconductor device with a strained channel
    Patent number: 7238581
    Abstract: A method of manufacturing a semiconductor device provides a semiconductor substrate with a gate and a number of source/drain regions on the semiconductor substrate. A layer containing a strain-inducing element is provided over the number of source/drain regions. The strain-inducing element is driven from the layer containing a strain-inducing element into the number of source/drain regions. A number of source/drains is formed in the number of source/drain regions.
    Type: Grant
    Filed: December 16, 2004
    Date of Patent: July 3, 2007
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: King Jien Chui, Ganesh Samudra, Yee Chia Yeo, Jinping Liu, Kheng Chok Tee, Wee Hong Phua, Lydia Wong
  • Method of manufacturing a semiconductor device with a strained channel
    Publication number: 20060030094
    Abstract: A method of manufacturing a semiconductor device provides a semiconductor substrate with a gate and a number of source/drain regions on the semiconductor substrate. A layer containing a strain-inducing element is provided over the number of source/drain regions. The strain-inducing element is driven from the layer containing a strain-inducing element into the number of source/drain regions. A number of source/drains is formed in the number of source/drain regions.
    Type: Application
    Filed: December 16, 2004
    Publication date: February 9, 2006
    Applicant: Chartered Semiconductor Manufacturing Ltd.
    Inventors: King Chui, Ganesh Samudra, Yee Yeo, Jinping Liu, Kheng Tee, Wee Phua, Lydia Wong