Abstract: An automated layout method allows designing advanced integrated circuits with design rules of high complexity. In particular, a hierarchical constrained layout process is applicable and useful for analog and mixed-signal integrated circuit designs and may be based on an incremental concurrent placement and routing. Use of constraints from multiple levels of a circuit description hierarchy allows computationally efficient processing of logical circuit increments and produces high-quality outcomes. Users such as circuit designers can exercise a high degree of predictability and control over the resulting physical layout construction by either user-specified or computer-generated constraints.

Abstract: An automated layout method allows designing advanced integrated circuits with design rules of high complexity. In particular, a hierarchical constrained layout process is applicable and useful for analog and mixed-signal integrated circuit designs and may be based on an incremental concurrent placement and routing. Use of constraints from multiple levels of a circuit description hierarchy allows computationally efficient processing of logical circuit increments and produces high-quality outcomes. Users such as circuit designers can exercise a high degree of predictability and control over the resulting physical layout construction by either user-specified or computer-generated constraints.

Abstract: Disclosed is a semiconductor standard cell architecture with local interconnect. The standard cell architecture includes a semiconductor substrate having diffusion regions that are designated for source and drain regions of a functional circuit. The standard cell also includes a polysilicon layer that is patterned to define gate electrodes and interconnections of the semiconductor standard cell architecture. In addition, the standard cell includes a local interconnect metallization layer that is patterned into a plurality of local interconnect metallization lines that are configured to be disposed over the semiconductor substrate and are further configured to substantially interconnect the source and drain regions and gate electrodes to define the functional circuit. The plurality of local interconnect metallization lines are further designed to incorporate local interconnect metallization pins that are connection points for interconnecting the functional circuit to another functional circuit.

Abstract: Disclosed is a semiconductor standard cell architecture with local interconnect. The standard cell architecture includes a semiconductor substrate having diffusion regions that are designated for source and drain regions of a functional circuit. The standard cell also includes a polysilicon layer that is patterned to define gate electrodes and interconnections of the semiconductor standard cell architecture. In addition, the standard cell includes a local interconnect metallization layer that is patterned into a plurality of local interconnect metallization lines that are configured to be disposed over the semiconductor substrate and are further configured to substantially interconnect the source and drain regions and gate electrodes to define the functional circuit. The plurality of local interconnect metallization lines are further designed to incorporate local interconnect metallization pins that are connection points for interconnecting the functional circuit to another functional circuit.

Abstract: Disclosed is a semiconductor standard cell architecture with local interconnect. The standard cell architecture includes a semiconductor substrate having diffusion regions that are designated for source and drain regions of a functional circuit. The standard cell also includes a polysilicon layer that is patterned to define gate electrodes and interconnections of the semiconductor standard cell architecture. In addition, the standard cell includes a local interconnect metallization layer that is patterned into a plurality of local interconnect metallization lines that are configured to be disposed over the semiconductor substrate and are further configured to substantially interconnect the source and drain regions and gate electrodes to define the functional circuit. The plurality of local interconnect metallization lines are further designed to incorporate local interconnect metallization pins that are connection points for interconnecting the functional circuit to another functional circuit.