Patents by Inventor Lynn Bos
Lynn Bos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10854251Abstract: This document describes techniques for authenticating an identity of a semiconductor component using a physical identifier. In some aspects, a physical identifier comprised of a region of features located indiscriminately within a surface of an encapsulated semiconductor component is fabricated. The physical identifier is then mapped. The map is then stored for use when authenticating the identity of the semiconductor component.Type: GrantFiled: December 15, 2017Date of Patent: December 1, 2020Assignee: Google LLCInventors: Andy Yang, Scott D. Johnson, Lynn Bos, Neal Mueller
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Patent number: 10331410Abstract: A true random number generator (TRNG) uses an analog circuit with a ring oscillator configured to collapse from an unstable oscillation state to a stable oscillation state at a random collapse time and counter counting a counter value representing the random collapse time. Various techniques are used to harden the TRNG including a truncator generating a true random number based on a truncation of the reference count value and a dedicated voltage regulator supplying power to the analog core including the ring oscillator. Techniques also include various solutions for drawing a constant current such as using a Gray code counter and adding noise current during and/or after the collapse event with a dummy inverter chain. Bit churning, bit obfuscation entropy enhancers and various post processing techniques may be employed to further harden the TRNG. An attack detection module may raise alerts when the TRNG is being attacked.Type: GrantFiled: November 9, 2016Date of Patent: June 25, 2019Assignee: Google LLCInventors: William Wesson, Scott Johnson, Karthika Periyathambi, Lynn Bos
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Publication number: 20190189171Abstract: This document describes techniques for authenticating an identity of a semiconductor component using a physical identifier. In some aspects, a physical identifier comprised of a region of features located indiscriminately within a surface of an encapsulated semiconductor component is fabricated. The physical identifier is then mapped. The map is then stored for use when authenticating the identity of the semiconductor component.Type: ApplicationFiled: December 15, 2017Publication date: June 20, 2019Applicant: Google LLCInventors: Andy Yang, Scott D. Johnson, Lynn Bos, Neal Mueller
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Publication number: 20180129476Abstract: A true random number generator (TRNG) uses an analog circuit with a ring oscillator configured to collapse from an unstable oscillation state to a stable oscillation state at a random collapse time and counter counting a counter value representing the random collapse time. Various techniques are used to harden the TRNG including a truncator generating a true random number based on a truncation of the reference count value and a dedicated voltage regulator supplying power to the analog core including the ring oscillator. Techniques also include various solutions for drawing a constant current such as using a Gray code counter and adding noise current during and/or after the collapse event with a dummy inverter chain. Bit churning, bit obfuscation entropy enhancers and various post processing techniques may be employed to further harden the TRNG. An attack detection module may raise alerts when the TRNG is being attacked.Type: ApplicationFiled: November 9, 2016Publication date: May 10, 2018Applicant: Google Inc.Inventors: William WESSON, Scott JOHNSON, Karthika PERIYATHAMBI, Lynn BOS
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Publication number: 20180107845Abstract: Provided are systems, methods, and apparatus for protecting an integrated circuit against invasive attacks and various forms of tampering. A defensive mechanism is an active physical security shield that includes an array of traces at a high metal of the integrated circuit, covering a high percentage of the surface area of that layer, and a collection of digital logic components that drive signals across the traces. The driving of the signals across the traces is done in an active manner such that a short, open, or stuck-at fault on any of the traces is detected within a very short period of time. The active security system is connected to or in communication with an alert response mechanism, such that a fault detected by the security system results in a signal being sent to the alert response mechanism.Type: ApplicationFiled: October 14, 2016Publication date: April 19, 2018Applicant: Google Inc.Inventors: William WESSON, Scott JOHNSON, Lynn BOS
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Patent number: 9946899Abstract: Provided are systems, methods, and apparatus for protecting an integrated circuit against invasive attacks and various forms of tampering. A defensive mechanism is an active physical security shield that includes an array of traces at a high metal of the integrated circuit, covering a high percentage of the surface area of that layer, and a collection of digital logic components that drive signals across the traces. The driving of the signals across the traces is done in an active manner such that a short, open, or stuck-at fault on any of the traces is detected within a very short period of time. The active security system is connected to or in communication with an alert response mechanism, such that a fault detected by the security system results in a signal being sent to the alert response mechanism.Type: GrantFiled: October 14, 2016Date of Patent: April 17, 2018Assignee: Google LLCInventors: William Wesson, Scott Johnson, Lynn Bos
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Patent number: 9171642Abstract: A circuit with a sampling network may include a pair of capacitors, where each of the capacitors has a first node and a second node; a first pair of switches communicatively coupling corresponding differential input voltage signals to the first node of each of the capacitors; and a second pair of switches communicatively coupling the second node of each of the capacitors to a common mode voltage source. Corresponding differential output voltage signals at the second node of each of the capacitors may be communicatively coupled using a differential switch. The second pair of switches may be coupled in parallel with the differential switch. A clock signal of the differential switch may be de-asserted prior to de-asserting corresponding clock signals for each of the second pair of switches.Type: GrantFiled: May 23, 2014Date of Patent: October 27, 2015Assignee: Google Inc.Inventors: Lynn Bos, Arnold Feldman, Shahriar Rabii
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Publication number: 20140253177Abstract: A circuit with a sampling network may include a pair of capacitors, where each of the capacitors has a first node and a second node; a first pair of switches communicatively coupling corresponding differential input voltage signals to the first node of each of the capacitors; and a second pair of switches communicatively coupling the second node of each of the capacitors to a common mode voltage source. Corresponding differential output voltage signals at the second node of each of the capacitors may be communicatively coupled using a differential switch. The second pair of switches may be coupled in parallel with the differential switch. A clock signal of the differential switch may be de-asserted prior to de-asserting corresponding clock signals for each of the second pair of switches.Type: ApplicationFiled: May 23, 2014Publication date: September 11, 2014Applicant: Google Inc.Inventors: Lynn Bos, Arnold Feldman, Shahriar Rabii
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Patent number: 8766669Abstract: A circuit with a sampling network may include a pair of capacitors, where each of the capacitors has a first node and a second node; a first pair of switches communicatively coupling corresponding differential input voltage signals to the first node of each of the capacitors; and a second pair of switches communicatively coupling the second node of each of the capacitors to a common mode voltage source. Corresponding differential output voltage signals at the second node of each of the capacitors may be communicatively coupled using a differential switch. The second pair of switches may be coupled in parallel with the differential switch. A clock signal of the differential switch may be de-asserted prior to de-asserting corresponding clock signals for each of the second pair of switches.Type: GrantFiled: September 10, 2012Date of Patent: July 1, 2014Assignee: Google Inc.Inventors: Lynn Bos, Arnold Feldman, Shahriar Rabii
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Patent number: 8094051Abstract: An analog to digital converting device is proposed for generating a digital output signal of an RF analog input signal. The device comprises a first analog to digital converter stage, a mixer, a second analog to digital converter stage and a digital filter. The first analog to digital converter stage generates a first and a second output signal. The first output signal is inputted in the filtering means. The second output signal is being down-converted to a signal with an intermediate frequency or DC. Thereafter, this down-converted signal is being fed to the second analog to digital converter stage. The digital output signal of this second stage is further processed together with the first digital output signal in the digital filter to a digital signal representative of the analog input signal.Type: GrantFiled: May 7, 2010Date of Patent: January 10, 2012Assignees: IMEC, Vrije Universiteit BrusselInventors: Lynn Bos, Julien Ryckaert, Geert Van der Plas, Jonathan Borremans
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Publication number: 20100283649Abstract: An analog to digital converting device is proposed for generating a digital output signal of an RF analog input signal. The device comprises a first analog to digital converter stage, a mixer, a second analog to digital converter stage and a digital filter. The first analog to digital converter stage generates a first and a second output signal. The first output signal is inputted in the filtering means. The second output signal is being down-converted to a signal with an intermediate frequency or DC. Thereafter, this down-converted signal is being fed to the second analog to digital converter stage. The digital output signal of this second stage is further processed together with the first digital output signal in the digital filter to a digital signal representative of the analog input signal.Type: ApplicationFiled: May 7, 2010Publication date: November 11, 2010Applicants: IMEC, VRIJE UNIVERSITEIT BRUSSELInventors: Lynn Bos, Julien Ryckaert, Geert Van der Plas, Jonathan Borremans