Abstract: A built in self test circuit for testing a phase lock loop (11). The built in self test circuitry comprises a pulse circuit (13), an And gate (19), a counter circuit (23), and an output multiplexer (24). The phase lock loop (11) receives a reference signal and generates an output signal. The pulse circuit (13) receives the reference signal and generates a pulse having a duration some multiple of the output signal of the phase lock loop. The And gate (19) receives the pulse output by pulse circuit (13) and the output signal of the phase lock loop (11) generating a string of pulses having the frequency of the output signal of the phase lock loop (11) for the duration of the pulse output by the pulse circuit (13). The counter circuit (23) receives the string of pulses and generates a count of the pulses. The count is compared to an expected count to determine the accuracy of the phase lock loop (11).