Patents by Inventor M. Cameron Watson

M. Cameron Watson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7706361
    Abstract: A multistage interconnect network (MIN) capable of supporting massive parallel processing, including point-to-point and multicast communications between processor modules (PMs) which are connected to the input and output ports of the network. The network is built using interconnected switch nodes arranged in 2 [logb N] stages, wherein b is the number of switch node input/output ports, N is the number of network input/output ports and [logb N] indicates a ceiling function providing the smallest integer not less than logb N. The additional stages provide additional paths between network input ports and network output ports, thereby enhancing fault tolerance and lessening contention.
    Type: Grant
    Filed: September 20, 2005
    Date of Patent: April 27, 2010
    Assignee: Teradata US, Inc.
    Inventors: Robert J. McMillen, M. Cameron Watson, David J. Chura
  • Patent number: 7080101
    Abstract: A method and apparatus enables partitioning of data to efficiently store and retrieve data relating to a database system (either a parallel or non-parallel database system). Such partitioning may be performed by receiving information associated with at least one characteristic of the data and performing an algorithm to divide the data into related data segments. The data segments may be stored in a distributive database system based on the characteristic associated with the data.
    Type: Grant
    Filed: December 1, 2000
    Date of Patent: July 18, 2006
    Assignee: NCR Corp.
    Inventors: M. Cameron Watson, Pierre Y. Colin
  • Patent number: 7058084
    Abstract: A multistage interconnect network (MIN) capable of supporting massive parallel processing, including point-to-point and multicast communications between processor modules (PMs) which are connected to the input and output ports of the network. The network is built using interconnected switch nodes arranged in 2 ?logb N? stages, wherein b is the number of switch node input/output ports, N is the number of network input/output ports and ?logb N? indicates a ceiling function providing the smallest integer not less than logb N. The additional stages provide additional paths between network input ports and network output ports, thereby enhancing fault tolerance and lessening contention.
    Type: Grant
    Filed: February 14, 2001
    Date of Patent: June 6, 2006
    Assignee: NCR Corporation
    Inventors: Robert J. McMillen, M. Cameron Watson, David J. Chura
  • Publication number: 20020010735
    Abstract: A multistage interconnect network (MIN) capable of supporting massive parallel processing, including point-to-point and multicast communications between processor modules (PMs) which are connected to the input and output ports of the network. The network is built using interconnected switch nodes arranged in 2 [logb N] stages, wherein b is the number of switch node input/output ports, N is the number of network input/output ports and [logb N] indicates a ceiling function providing the smallest integer not less than logb N. The additional stages provide additional paths between network input ports and network output ports, thereby enhancing fault tolerance and lessening contention.
    Type: Application
    Filed: February 14, 2001
    Publication date: January 24, 2002
    Inventors: Robert J. McMillen, M. Cameron Watson, David J. Chura
  • Patent number: 6243361
    Abstract: A multistage interconnect network (MIN) capable of supporting massive parallel processing, including point-to-point and multicast communications between processor modules (PMs) which are connected to the input and output ports of the network. The network is built using interconnected switch nodes arranged in 2 |logb N| stages, wherein b is the number of switch node input/output ports, N is the number of network input/output ports and |logb N| indicates a ceiling function providing the smallest integer not less than logb N. The additional stages provide additional paths between network input ports and network output ports, thereby enhancing fault tolerance and lessening contention.
    Type: Grant
    Filed: November 10, 1998
    Date of Patent: June 5, 2001
    Assignee: NCR Corporation
    Inventors: Robert J. McMillen, M. Cameron Watson, David J. Chura
  • Patent number: 5872904
    Abstract: A multistage interconnect network (MIN) capable of supporting massive parallel processing, including point-to-point and multicast communications between processor modules (PMs) which are connected to the input and output ports of the network. The network is built using interconnected switch nodes arranged in 2 .left brkt-top. log.sub.b N .right brkt-top. stages, wherein b is the number of switch node input/output ports, N is the number of network input/output ports and .left brkt-top. log.sub.b N .right brkt-top. indicates a ceiling function providing the smallest integer not less than log.sub.b N. The additional stages provide additional paths between network input ports and network output ports, thereby enhancing fault tolerance and lessening contention.
    Type: Grant
    Filed: May 24, 1996
    Date of Patent: February 16, 1999
    Assignee: NCR Corporation
    Inventors: Robert J. McMillen, M. Cameron Watson, David J. Chura
  • Patent number: 5522046
    Abstract: A multistage interconnect network (MIN) capable of supporting massive parallel processing, including point-to-point and multicast communications between processor modules (PMs) which are connected to the input and output ports of the network. The network is built using interconnected switch nodes arranged in 2 log.sub.b N stages, wherein b is the number of switch node input/output ports, N is the number of network input/output ports and log.sub.b N indicates a ceiling function providing the smallest integer not less than log.sub.b N. The additional stages provide additional paths between network input ports and network output ports, thereby enhancing fault tolerance and lessening contention.
    Type: Grant
    Filed: June 3, 1994
    Date of Patent: May 28, 1996
    Assignee: NCR Corporation
    Inventors: Robert J. McMillen, M. Cameron Watson, David J. Chura
  • Patent number: 5321813
    Abstract: A multistage interconnect network (MIN) capable of supporting massive parallel processing, including point-to-point and multicast communications between processor modules (PMs) which are connected to the input and output ports of the network. The network is built using interconnected switch nodes arranged in 2 log.sub.b N stages, wherein b is the number of switch node input/output ports, N is the number of network input/output ports and log.sub.b N indicates a ceiling function providing the smallest integer not less than log.sub.b N. The additional stages provide additional paths between network input ports and network output ports, thereby enhancing fault tolerance and lessening contention.
    Type: Grant
    Filed: May 1, 1991
    Date of Patent: June 14, 1994
    Assignee: Teradata Corporation
    Inventors: Robert J. McMillen, M. Cameron Watson, David J. Chura
  • Patent number: 5303244
    Abstract: A fault tolerant disk drive matrix comprises a plurality of disk drives. A mapping method associates a subset of the disk drives with a logical RAID-5 array. Each of the disk drives in the matrix may be associated with a plurality of different logical RAID-5 arrays. Logical units of data are subdivided into blocks and stored in an interleaved manner across the disk drives of the logical RAID-5 array. The arrangement of data and parity blocks on the logical RAID-5 arrays within the matrix reduces throughput degradation when a disk drive fails. In the event of a disk drive failure, data blocks stored on the failed disk drive can be reconstructed using redundancy blocks and data blocks from the surviving disk drives within the logical RAID-5 array. Replacement disk drives may also be provided to substitute for the failed disk drive in the logical RAID-5 array.
    Type: Grant
    Filed: March 1, 1991
    Date of Patent: April 12, 1994
    Assignees: Teradata, NCR Corporation
    Inventor: M. Cameron Watson
  • Patent number: 5303383
    Abstract: A multistage interconnect network (MIN) capable of supporting massive parallel processing, including point-to-point and multicast communications between processor modules (PMs) which are connected to the input and output ports of the network. The network is built using interconnected switch nodes arranged in 2 log.sub.b N stages, wherein b is the number of switch node input/output ports, N is the number of network input/output ports and log.sub.b N indicates a ceiling function providing the smallest integer not less than log.sub.b N. The additional stages provide additional paths between network input ports and network output ports, thereby enhancing fault tolerance and lessening contention.
    Type: Grant
    Filed: August 14, 1992
    Date of Patent: April 12, 1994
    Assignee: NCR Corporation
    Inventors: Philip M. Neches, Robert J. McMillen, M. Cameron Watson, David J. Chura