Patents by Inventor M. Rao

M. Rao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180039627
    Abstract: Personalized content is generated from different media items using a content index. The content index is generated or updated by identifying segments of media items that are of particular interest to users. User interactions with the media items are analyzed and metadata of segments of media items that are determined to be of particular interest to the users is recorded. The parameters associated with a request for personalized content for a user are matched with the recorded metadata to identify relevant media items or segments of media items which are transmitted to the user as the personalized content.
    Type: Application
    Filed: October 16, 2017
    Publication date: February 8, 2018
    Inventors: David REILEY, Justin M. RAO, Michael SCHWARTZ, Andrzej SKRZYPACZ
  • Patent number: 9883027
    Abstract: A contactability of a user can be maintained by identifying a secondary device and causing a contact device to establish a communication session with the secondary device when a primary device becomes unavailable. In some embodiments, when a power level of a primary device falls below a threshold, the primary device can identify a secondary device previously associated with the primary device. The secondary device can receive a signal periodically from the primary device. In response to ceasing to receive the signal that is being sent periodically from the primary device, the secondary device in some embodiments can send a notification to a contact device to inform the contact device to send a communication request to the secondary device. The secondary device can receive the communication request from the contact device and establish a communication session with the contact device.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: January 30, 2018
    Assignee: Apple Inc.
    Inventors: Swapnil R. Dave, Kaustubh M. Rao
  • Publication number: 20180001262
    Abstract: A method for controlling treatment of an industrial water system is disclosed. The method comprises the steps of providing an apparatus for controlling delivery of at least one treatment chemical, the apparatus comprising at least one sensor and an electronic input/output device carrying out a protocol; measuring a parameter of the industrial water system using the at least one sensor; relaying the measured parameter to the electronic device; adjusting the protocol based on the measured parameter; delivering a concentrated treatment chemical into a stream of the industrial water system according to the adjusted protocol, the concentrated treatment chemical comprising an active ingredient, the active ingredient traced as necessary, the active ingredient having a concentration; repeating the measuring, the adjusting, and the delivering; and optionally repeating the steps for n-number of parameters, n-number of active ingredients, and/or n-number of concentrated treatment chemicals.
    Type: Application
    Filed: September 15, 2017
    Publication date: January 4, 2018
    Applicant: Ecolab USA Inc.
    Inventors: Narasimha M. Rao, Steven R. Hatch, William A. Von Drasek
  • Publication number: 20170364421
    Abstract: A method, executed by a computer, includes pairing a first core with a second core to form a first core group, wherein each core of the group has a plurality of functional units, transferring instructions received by the first core to the second core for execution via a first inter-core communication bus, and executing the instructions on the second core. A computer system and computer program product corresponding to the above method are also disclosed herein.
    Type: Application
    Filed: June 15, 2016
    Publication date: December 21, 2017
    Inventors: Manoj Dusanapudi, Prasanna Jayaraman, Rahul M. Rao
  • Publication number: 20170365362
    Abstract: A method includes configuring an integrated circuit comprising one or more registers to provide a free running clock in the integrated circuit, simulating N clock cycles in the circuit to provide performance results for one or more registers in the circuit, wherein N is a selected number of staging levels, selecting one of the one or more registers, comparing the performance results for the selected register to performance results for each of the remaining registers to provide one or more equivalent delay candidate registers, and verifying each of the one or more equivalent delay candidate registers to provide one or more confirmed equivalent delay registers. A corresponding computer program product and computer system are also disclosed.
    Type: Application
    Filed: July 28, 2017
    Publication date: December 21, 2017
    Inventors: Raj Kumar Gajavelly, Ashutosh Misra, Pradeep Kumar Nalla, Rahul M. Rao
  • Publication number: 20170344678
    Abstract: A computer-implemented method includes receiving a unit, wherein each unit includes one or more blocks. The computer-implemented method further includes selecting one or more input pins for each of said one or more blocks. The computer-implemented method further includes assigning a numerical value to each of said one or more input pins to yield at least one numerical sequence. The computer-implemented method further includes, for each numerical sequence of the at least one numerical sequence, performing a check on the numerical sequence to yield a number of fails. The computer-implemented method further includes determining a simulation condition for power modeling of the unit based on optimizing a numerical sequence with respect to the number of fails. The computer-implemented method further includes determining a number of design errors of the unit based on the simulation condition. A corresponding computer system and computer program product are also disclosed.
    Type: Application
    Filed: August 16, 2017
    Publication date: November 30, 2017
    Inventors: Anand Haridass, Arun Joseph, Pradeep Kumar Nalla, Rahul M. Rao
  • Publication number: 20170336918
    Abstract: Devices for sensing touch on a surface using a minimum depth-value surface characterization, including associated methods, are disclosed and described.
    Type: Application
    Filed: May 22, 2016
    Publication date: November 23, 2017
    Applicant: Intel Corporation
    Inventors: David R. Holman, Kip C. Killpack, Brandon Gavino, Vinay K. Nooji, Abhay A. Dharmadhikari, Vijay M. Rao
  • Publication number: 20170337312
    Abstract: A processor may receive a transistor level integrated circuit (IC) design to be modelled. The processor may determine that the transistor level IC design has a first stage and a second stage. The processor may determine a first cross-current effective capacitance of the first stage and a second cross-current effective capacitance of the second stage. The processor may then determine a cross-current effective capacitance for the transistor level IC design by accumulating the first and second cross-current effective capacitances.
    Type: Application
    Filed: August 14, 2017
    Publication date: November 23, 2017
    Inventors: Arun Joseph, Arya Madhusoodanan, Rahul M. Rao, Suriya T. Skariah
  • Publication number: 20170337311
    Abstract: A processor may receive a transistor level integrated circuit (IC) design to be modelled. The processor may determine that the transistor level IC design has a first stage and a second stage. The processor may determine a first cross-current effective capacitance of the first stage and a second cross-current effective capacitance of the second stage. The processor may then determine a cross-current effective capacitance for the transistor level IC design by accumulating the first and second cross-current effective capacitances.
    Type: Application
    Filed: August 14, 2017
    Publication date: November 23, 2017
    Inventors: Arun Joseph, Arya Madhusoodanan, Rahul M. Rao, Suriya T. Skariah
  • Publication number: 20170315605
    Abstract: A method for analyzing power in a circuit includes identifying equivalent elements in a source netlist representing the circuit. Abstract elements are formed combining the equivalent elements of the source netlist. A reduced netlist is formed, substituting the abstract elements in the reduced netlist for the collective equivalent elements in the source netlist. Metrics or properties associated with equivalent elements of the source netlist are combined and associated, in the reduced netlist, with the abstract elements. The reduced netlist can be analyzed with results equivalent to analyzing the source netlist.
    Type: Application
    Filed: December 20, 2016
    Publication date: November 2, 2017
    Inventors: Arun Joseph, Rahul M. Rao
  • Publication number: 20170316119
    Abstract: A method for analyzing power in a circuit includes identifying equivalent elements in a source netlist representing the circuit. Abstract elements are formed combining the equivalent elements of the source netlist. A reduced netlist is formed, substituting the abstract elements in the reduced netlist for the collective equivalent elements in the source netlist. Metrics or properties associated with equivalent elements of the source netlist are combined and associated, in the reduced netlist, with the abstract elements. The reduced netlist can be analyzed with results equivalent to analyzing the source netlist.
    Type: Application
    Filed: April 27, 2016
    Publication date: November 2, 2017
    Inventors: Arun Joseph, Rahul M. Rao
  • Patent number: 9792285
    Abstract: Personalized content is generated from different media items using a content index. The content index is generated or updated by identifying segments of media items that are of particular interest to users. User interactions with the media items are analyzed and metadata of segments of media items that are determined to be of particular interest to the users is recorded. The parameters associated with a request for personalized content for a user are matched with the recorded metadata to identify relevant media items or segments of media items which are transmitted to the user as the personalized content.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: October 17, 2017
    Assignee: EXCALIBUR IP, LLC
    Inventors: David Reiley, Michael Schwarz, Justin M. Rao, Andrzej Skrzypacz
  • Publication number: 20170285745
    Abstract: This disclosure is directed to a system to provide tactile feedback during non-contact interaction. A system may comprise at least display circuitry, sensing circuitry, tactile feedback circuitry and processing circuitry. The processing circuitry may cause the display circuitry to present a user interface. The sensing circuitry may sense when a body part of a user (e.g., a hand, a finger, etc.) is proximate to the user interface and may generate position data based on a sensed position of the body part. The processing circuitry may determine a relative position of the body part with respect to the user interface based on the position data, and may determine if the body part is interacting with the user interface based on the relative position. If it is determined that the body part is interacting with the user interface, the processing circuitry may cause the tactile feedback circuitry to generate directional feedback.
    Type: Application
    Filed: March 29, 2016
    Publication date: October 5, 2017
    Applicant: Intel Corporation
    Inventors: KEVIN J. DORAN, STEPHEN H. HALL, MURALI VEERAMONEY, VIJAY M. RAO, ROYCE FERNALD
  • Patent number: 9769768
    Abstract: Various methods and devices are provided to address the need for reducing interference in heterogeneous wireless networks. In one apparatus, a network node (500) that includes a transceiver (502) and a processing unit (501) is provided. The processing unit is configured to transmit, via the transceiver, downlink signaling at a primary power spectral density (PSD) level and to also transmit, via the transceiver, a group of control channel elements (CCEs) on a physical downlink control channel (PDCCH) at a reduced PSD level, the reduced PSD level being less than the primary PSD level.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: September 19, 2017
    Assignee: Alcatel-Lucent USA Inc.
    Inventor: Anil M Rao
  • Patent number: 9754058
    Abstract: A processor may receive a transistor level integrated circuit (IC) design to be modelled. The processor may determine that the transistor level IC design has a first stage and a second stage. The processor may determine a first cross-current effective capacitance of the first stage and a second cross-current effective capacitance of the second stage. The processor may then determine a cross-current effective capacitance for the transistor level IC design by accumulating the first and second cross-current effective capacitances.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: September 5, 2017
    Assignee: International Business Machines Corporation
    Inventors: Arun Joseph, Arya Madhusoodanan, Rahul M. Rao, Suriya T. Skariah
  • Publication number: 20170249322
    Abstract: Multiple mobile devices can be enabled to collaboratively search online information databases for results that may be interesting to all of them. Such search results can involve places of interest at which all of the search participants can conveniently meet due to the locations of those results being near to all of the search participants, for example.
    Type: Application
    Filed: March 2, 2017
    Publication date: August 31, 2017
    Inventors: Swapnil R Dave, Kaustubh M. Rao
  • Publication number: 20170235856
    Abstract: A computer-implemented method includes receiving a unit, wherein each unit includes one or more blocks. The computer-implemented method further includes selecting one or more input pins for each of said one or more blocks. The computer-implemented method further includes assigning a numerical value to each of said one or more input pins to yield at least one numerical sequence. The computer-implemented method further includes, for each numerical sequence of the at least one numerical sequence, performing a check on the numerical sequence to yield a number of fails. The computer-implemented method further includes determining a simulation condition for power modeling of the unit based on optimizing a numerical sequence with respect to the number of fails. The computer-implemented method further includes determining a number of design errors of the unit based on the simulation condition. A corresponding computer system and computer program product are also disclosed.
    Type: Application
    Filed: February 11, 2016
    Publication date: August 17, 2017
    Inventors: Anand Haridass, Arun Joseph, Pradeep Kumar Nalla, Rahul M. Rao
  • Publication number: 20170236332
    Abstract: A mixed-reality display device comprises an input system, a display, and a graphics processor. The input system is configured to receive a parameter value, the parameter value being one of a plurality of values of a predetermined range receivable by the input system. The display is configured to display virtual image content that adds an augmentation to a real-world environment viewed by a user of the mixed-reality display device. The graphics processor is coupled operatively to the input system and to the display; it is configured to render the virtual image content so as to variably change the augmentation, to variably change a perceived realism of the real world environment in correlation to the parameter value.
    Type: Application
    Filed: October 21, 2016
    Publication date: August 17, 2017
    Inventors: Alex Kipman, Purnima M. Rao, Rebecca Haruyama, Shih-Sang Carnaven Chiu, Stuart Mayhew, Oscar E. Murillo, Carlos Fernando Faria Costa
  • Patent number: 9697306
    Abstract: A computer program product includes program instructions to: Receive a unit including register transfer level content for a component of an integrated circuit and one or more IP blocks; Select one or more input pins for each IP block; Assign a numerical value of either zero or one to each of the one or more input pins to yield at least one numerical sequence; For each numerical sequence, perform a check to yield a number of fails, wherein the check is formal verification of each of the one or more IP blocks; Determine a simulation condition for power modeling of the unit based on optimizing a numerical sequence with respect to the number of fails; Set the one or more input pins to the simulation condition for power modeling of the unit; and Determine a number of design errors of the unit based on the simulation condition.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: July 4, 2017
    Assignee: International Business Machines Corporation
    Inventors: Anand Haridass, Arun Joseph, Pradeep Kumar Nalla, Rahul M. Rao
  • Publication number: 20170132343
    Abstract: A processor may receive a transistor level integrated circuit (IC) design to be modelled. The processor may determine that the transistor level IC design has a first stage and a second stage. The processor may determine a first cross-current effective capacitance of the first stage and a second cross-current effective capacitance of the second stage. The processor may then determine a cross-current effective capacitance for the transistor level IC design by accumulating the first and second cross-current effective capacitances.
    Type: Application
    Filed: August 23, 2016
    Publication date: May 11, 2017
    Inventors: Arun Joseph, Arya Madhusoodanan, Rahul M. Rao, Suriya T. Skariah