Patents by Inventor M. Wasiur RASHID

M. Wasiur RASHID has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10430356
    Abstract: Embodiments of the present invention set forth techniques for resolving page faults associated with a copy engine. A copy engine within a parallel processor receives a copy operation that includes a set of copy commands. The copy engine executes a first copy command included in the set of copy commands that results in a page fault. The copy engine stores the set of copy commands to the memory. At least one advantage of the disclosed techniques is that the copy engine can perform copy operations that involve source and destination memory pages that are not pinned, leading to reduced memory demand and greater flexibility.
    Type: Grant
    Filed: April 28, 2017
    Date of Patent: October 1, 2019
    Assignee: NVIDIA CORPORATION
    Inventors: M. Wasiur Rashid, Jonathon Evans, Gary Ward, Philip Browning Johnson
  • Patent number: 10275275
    Abstract: A copy subsystem within a processor includes a set of logical copy engines and a set of physical copy engines. Each logical copy engine corresponds to a different command stream implemented by a device driver, and each logical copy engine is configured to receive copy commands via the corresponding command stream. When a logical copy engine receives a copy command, the logical copy engine distributes the command, or one or more subcommands derived from the command, to one or more of the physical copy engines. The physical copy engines can perform multiple copy operations in parallel with one another, thereby allowing the bandwidth of the communication link(s) to be saturated.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: April 30, 2019
    Assignee: NVIDIA CORPORATION
    Inventors: M. Wasiur Rashid, Gary Ward, Wei-Je Robert Huang, Philip Browning Johnson
  • Patent number: 10180916
    Abstract: A copy subsystem within a processor includes a set of logical copy engines and a set of physical copy engines. Each logical copy engine corresponds to a different command stream implemented by a device driver, and each logical copy engine is configured to receive copy commands via the corresponding command stream. When a logical copy engine receives a copy command, the logical copy engine distributes the command, or one or more subcommands derived from the command, to one or more of the physical copy engines. The physical copy engines can perform multiple copy operations in parallel with one another, thereby allowing the bandwidth of the communication link(s) to be saturated.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: January 15, 2019
    Assignee: NVIDIA CORPORATION
    Inventors: M. Wasiur Rashid, Gary Ward, Wei-Je Robert Huang, Philip Browning Johnson
  • Publication number: 20180314431
    Abstract: Embodiments of the present invention set forth techniques for resolving page faults associated with a copy engine. A copy engine within a parallel processor receives a copy operation that includes a set of copy commands. The copy engine executes a first copy command included in the set of copy commands that results in a page fault. The copy engine stores the set of copy commands to the memory. At least one advantage of the disclosed techniques is that the copy engine can perform copy operations that involve source and destination memory pages that are not pinned, leading to reduced memory demand and greater flexibility.
    Type: Application
    Filed: April 28, 2017
    Publication date: November 1, 2018
    Inventors: M. Wasiur Rashid, Jonathon EVANS, Gary Ward, Philip Browning Johnson
  • Patent number: 10095526
    Abstract: A multi-threaded processing unit includes a hardware pre-processor coupled to one or more processing engines (e.g., copy engines, GPCs, etc.) that implement pre-emption techniques by dividing tasks into smaller subtasks and scheduling subtasks on the processing engines based on the priority of the tasks. By limiting the size of the subtasks, higher priority tasks may be executed quickly without switching the context state of the processing engine. Tasks may be subdivided based on a threshold size or by taking into account other consideration such as physical boundaries of the memory system.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: October 9, 2018
    Assignee: NVIDIA CORPORATION
    Inventors: Samuel H. Duncan, Gary Ward, M. Wasiur Rashid, Lincoln G. Garlick, Wojciech Jan Truty
  • Publication number: 20170161099
    Abstract: A copy subsystem within a processor includes a set of logical copy engines and a set of physical copy engines. Each logical copy engine corresponds to a different command stream implemented by a device driver, and each logical copy engine is configured to receive copy commands via the corresponding command stream. When a logical copy engine receives a copy command, the logical copy engine distributes the command, or one or more subcommands derived from the command, to one or more of the physical copy engines. The physical copy engines can perform multiple copy operations in parallel with one another, thereby allowing the bandwidth of the communication link(s) to be saturated.
    Type: Application
    Filed: December 3, 2015
    Publication date: June 8, 2017
    Inventors: M. Wasiur Rashid, Gary Ward, Wei-Je Robert Huang, Philip Browning Johnson
  • Publication number: 20170161100
    Abstract: A copy subsystem within a processor includes a set of logical copy engines and a set of physical copy engines. Each logical copy engine corresponds to a different command stream implemented by a device driver, and each logical copy engine is configured to receive copy commands via the corresponding command stream. When a logical copy engine receives a copy command, the logical copy engine distributes the command, or one or more subcommands derived from the command, to one or more of the physical copy engines. The physical copy engines can perform multiple copy operations in parallel with one another, thereby allowing the bandwidth of the communication link(s) to be saturated.
    Type: Application
    Filed: December 3, 2015
    Publication date: June 8, 2017
    Inventors: M. Wasiur Rashid, Gary Ward, Wei-Je Robert Huang, Philip Browning Johnson
  • Publication number: 20140109102
    Abstract: A multi-threaded processing unit includes a hardware pre-processor coupled to one or more processing engines (e.g., copy engines, GPCs, etc.) that implement pre-emption techniques by dividing tasks into smaller subtasks and scheduling subtasks on the processing engines based on the priority of the tasks. By limiting the size of the subtasks, higher priority tasks may be executed quickly without switching the context state of the processing engine. Tasks may be subdivided based on a threshold size or by taking into account other consideration such as physical boundaries of the memory system.
    Type: Application
    Filed: October 12, 2012
    Publication date: April 17, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Samuel H. Duncan, Gary WARD, M. Wasiur RASHID, Lincoln G. GARLICK, Wojciech Jan Truty