Abstract: Embodiments of an IC device are disclosed. In some embodiments, an integrated circuit (IC) device, includes: an first active semiconductor layer that includes first active semiconductor device regions; a second active semiconductor layer that includes active semiconductor regions, the second active semiconductor layer being connected to the first active semiconductor layer and being positioned over the first active semiconductor layer; a first redistribution layer positioned over the second active conductor layer, the first redistribution layer is electrically connected to the first active semiconductor layer and the second active semiconductor layer; a passivation layer positioned on the first redistribution layer; a second redistribution layer positioned over the passivation layer, wherein the second redistribution layer is electrically connected to the first redistribution layer.

Abstract: The present disclosure relates to an integrated circuit module with electromagnetic shielding. The integrated circuit module includes a die with an input/output (I/O) port at a bottom surface of the die, a mold compound partially encapsulating the die and leaving the bottom surface of the die exposed, a first dielectric pattern over the bottom surface of the die, a redistribution structure over the first dielectric pattern, and a shielding structure. The I/O port at the bottom surface of the die is exposed through the first dielectric pattern. The redistribution structure includes a shield connected element that is coupled to the I/O port and extends laterally beyond the die. The shielding structure resides over a top surface of the mold compound, extends along side surfaces of the mold compound, and is in contact with the shield connected element. Herein, the shielding structure does not extend vertically beyond the shield connected element.

Abstract: The present disclosure relates to an integrated circuit module with electromagnetic shielding. The integrated circuit module includes a die with an input/output (I/O) port at a bottom surface of the die, a mold compound partially encapsulating the die and leaving the bottom surface of the die exposed, a first dielectric pattern over the bottom surface of the die, a redistribution structure over the first dielectric pattern, and a shielding structure. The I/O port at the bottom surface of the die is exposed through the first dielectric pattern. The redistribution structure includes a shield connected element that is coupled to the I/O port and extends laterally beyond the die. The shielding structure resides over a top surface of the mold compound, extends along side surfaces of the mold compound, and is in contact with the shield connected element. Herein, the shielding structure does not extend vertically beyond the shield connected element.

Abstract: The present disclosure integrates electromagnetic shielding into a wafer level fan-out packaging process. First, a mold wafer having multiple modules is provided. Each module includes a die with an I/O port and is surrounded by an inter-module area. A redistribution structure that includes a shield connected element coupled to the I/O port of each module is formed over a bottom surface of the mold wafer. The shield connected element extends laterally from the I/O port into the inter-module area for each module. Next, the mold wafer is sub-diced at each inter-module area to create a cavity. A portion of the shield connected element is then exposed through the bottom of each cavity. A shielding structure is formed over a top surface of the mold wafer and exposed faces of each cavity. The shielding structure is in contact with the shield connected element.

Abstract: The present disclosure integrates electromagnetic shielding into a wafer level fan-out packaging process. First, a mold wafer having multiple modules is provided. Each module includes a die with an I/O port and is surrounded by an inter-module area. A redistribution structure that includes a shield connected element coupled to the I/O port of each module is formed over a bottom surface of the mold wafer. The shield connected element extends laterally from the I/O port into the inter-module area for each module. Next, the mold wafer is sub-diced at each inter-module area to create a cavity. A portion of the shield connected element is then exposed through the bottom of each cavity. A shielding structure is formed over a top surface of the mold wafer and exposed faces of each cavity. The shielding structure is in contact with the shield connected element.

Abstract: An integrated circuit package system is provided including forming a wafer having a back side and an active side, forming a recess in the wafer from the back side, forming a cover in the recess, and singulating the wafer at the recess filled with the cover.

Abstract: An integrated circuit package-on-package stacking system includes a leadframe interposer including: a leadframe having a lead; a molded base on a portion of the lead for only supporting the lead; and the leadframe interposer singulated from the leadframe, wherein the lead is bent to support a stack-up height.

Abstract: A method of laser-marking a semiconductor device involves providing a semiconductor wafer having a plurality of solder bumps formed on contact pads disposed on its active surface. The solder bumps have a diameter of about 250-280 ?m. A backgrinding tape is applied over the solder bumps. The tape is translucent to optical images. A backside of the semiconductor wafer, opposite the active surface, undergoes grinding to reduce wafer thickness. The backside of the semiconductor wafer is laser-marked while the tape remains applied to the solder bumps. The laser-marking system including an optical recognition device, control system, and laser. The optical recognition device reads patterns on the active surface through the tape to control the laser. The tape reduces wafer warpage during laser-marking to about 0.3-0.5 mm. The tape is removed after laser-marking the backside of the semiconductor wafer.

Abstract: An integrated circuit package-on-package stacking system includes a leadframe interposer including: a leadframe having a lead; a molded base on a portion of the lead for only supporting the lead; and the leadframe interposer singulated from the leadframe, wherein the lead is bent to support a stack-up height.

Abstract: An integrated circuit package-on-package stacking method includes forming a leadframe interposer including: forming a leadframe having a lead; forming a molded base only supporting the lead; and singulating the leadframe interposer from the leadframe.

Abstract: An integrated circuit package-on-package stacking method includes forming a leadframe interposer including: forming a leadframe having a lead; forming a molded base only supporting the lead; and singulating the leadframe interposer from the leadframe.

Abstract: An integrated circuit package-on-package stacking system is provided including, forming a leadframe interposer including: forming a leadframe; forming a molded base on the leadframe; and singulating the leadframe interposer from the leadframe.

Abstract: A method of laser-marking a semiconductor device involves providing a semiconductor wafer having a plurality of solder bumps formed on contact pads disposed on its active surface. The solder bumps have a diameter of about 250-280 ?m. A backgrinding tape is applied over the solder bumps. The tape is translucent to optical images. A backside of the semiconductor wafer, opposite the active surface, undergoes grinding to reduce wafer thickness. The backside of the semiconductor wafer is laser-marked while the tape remains applied to the solder bumps. The laser-marking system including an optical recognition device, control system, and laser. The optical recognition device reads patterns on the active surface through the tape to control the laser. The tape reduces wafer warpage during laser-marking to about 0.3-0.5 mm. The tape is removed after laser-marking the backside of the semiconductor wafer.

Abstract: An integrated circuit package system is provided including forming a wafer having a back side and an active side, forming a recess in the wafer from the back side, forming a cover in the recess, and singulating the wafer at the recess filled with the cover.

Abstract: An integrated circuit package-on-package stacking system is provided including, forming a leadframe interposer including: forming a leadframe; forming a molded base on the leadframe; and singulating the leadframe interposer from the leadframe.