Abstract: Systems are provided for a cooling system for an electric vehicle. In one example, a system includes a plate arranged between separate circuit boards. The plate directly cools one of the circuit boards and block thermal communication between the circuit boards.

Abstract: An inverter assembly including a phase-control chamber and a direct current (DC) chamber. The phase-control chamber includes a direct current (DC) link capacitor electrically connected a control circuit board via multiple connectors. The DC chamber includes a ferrite filter fixed to a DC bus bar via a support component.

Abstract: An inverter is provided that includes a direct current (DC) bus bar assembly positioned within a DC chamber in the housing is provided herein. The inverter further includes a gate-driver circuit board included in a phase-control chamber in the housing, and an external communication interface in electronic communication with a power control circuit board and positioned in an external communication chamber in the housing. The DC chamber, the phase-control chamber, and the external communication chamber have varying levels of electromagnetic interference (EMI).

Abstract: Methods and systems are provided for modulating undesired electric-motor braking. Based upon the detection of an inverter degradation event, one of a first gate driver and a second gate driver (e.g., a high gate driver and a low gate driver, such as for one phase of an inverter) may be asserted in an alternating manner while the other of the first gate driver and a second gate driver is de-asserted, and the first gate driver and second gate driver may then be provided to a power switch circuitry. The alternating assertion of the one of the first gate driver and the second gate driver may be associated with a higher-speed state, and the de-assertion of both the first gate driver and the second gate driver may be associated with a lower-speed state.

Abstract: Methods and systems are provided for modulating undesired electric-motor braking. Based upon the detection of an inverter degradation event, one of a first gate driver and a second gate driver (e.g., a high gate driver and a low gate driver, such as for one phase of an inverter) may be asserted in an alternating manner while the other of the first gate driver and a second gate driver is de-asserted, and the first gate driver and second gate driver may then be provided to a power switch circuitry. The alternating assertion of the one of the first gate driver and the second gate driver may be associated with a higher-speed state, and the de-assertion of both the first gate driver and the second gate driver may be associated with a lower-speed state.

Abstract: The present disclosure relates to a circuit for providing a current from a source to a load. A commutation cell includes a main switch that controls a voltage applied by the source to the load. An opposite switch maintains the current in the load when the load is disconnected from the source by the main switch. The opposite switch returns the load current to the main switch when the main switch connects again the load to the source. The disclosed circuit configuration reduces recovery current, losses and electromagnetic losses. A synchronizing controller controls opening and closing sequences of the main switch and of the opposite switch. The disclosed circuit can provide a DC-DC voltage converter. Combining two such circuits can provide a DC-AC voltage converter.

Abstract: The present disclosure relates to a commutation cell and to a compensation circuit for limiting overvoltage across the power electronic switch of the commutation cell and for limiting a recovery current in a freewheel diode of the commutation cell. The power electronic switch has a parasitic emitter inductance. A variable gain compensation circuit generates a feedback from a voltage generated across the parasitic inductance of the emitter of the power switch at turn-on or turn-off of the power electronic switch. The compensation circuit provides the feedback to a control of the power electronic switch to reduce the voltage generated on the parasitic emitter inductance. A power converter including the commutation cell with the compensation circuit is also disclosed.

Abstract: The present disclosure relates to a power converter configured for limiting switching overvoltage. The power converter comprises a bottom commutation cell that includes a bottom power electronic switch and a bottom compensation circuit connected to a bottom parasitic inductance. The bottom compensation circuit applies a sample of the voltage induced across the bottom parasitic inductance at turn-off of the bottom power electronic switch to the reference node of the bottom gate driver. The power converter also comprises a top commutation cell that includes top power electronic switch and a top compensation circuit connected to the bottom parasitic inductance. The top compensation circuit applies a sample of the voltage induced across the bottom parasitic emitter upon turn-off of the top power electronic switch to the reference node of the top gate driver.

Abstract: A physical topology for receiving top and bottom power electronic switches comprises a top collector trace connected to a positive voltage power supply tab and having a connection area for a collector of a top power electronic switch, a bottom emitter trace connected to a negative voltage power supply tab and having a connection area for an emitter of the bottom power electronic switch, and a middle trace connected to a load tab and having a connection area for an emitter of the top power electronic switch and a connection area for a collector of the bottom power electronic switch. Sampling points are provided on the traces for voltages on the emitters of the top and bottom power electronic switches, on the trace for voltage of the collector of the bottom power electronic switch, and on the negative voltage power supply tab. The topology defines parasitic inductances.

Abstract: A turn-off overvoltage limiting for IGBT is described herein. The injection of a sample of the overvoltage across the IGBT in the gate drive to slow down the slope of the gate voltage decrease only during the overvoltage above a predetermined value is described herein. Techniques to increase the parasitic inductance to allow the control to limit an overvoltage at turn off of the second IGBT are also described herein.

Abstract: The present disclosure relates to a circuit for providing a current from a source to a load. A commutation cell includes a main switch that controls a voltage applied by the source to the load. An opposite switch maintains the current in the load when the load is disconnected from the source by the main switch. The opposite switch returns the load current to the main switch when the main switch connects again the load to the source. The disclosed circuit configuration reduces recovery current, losses and electromagnetic losses. A synchronizing controller controls opening and closing sequences of the main switch and of the opposite switch. The disclosed circuit can provide a DC-DC voltage converter. Combining two such circuits can provide a DC-AC voltage converter.

Abstract: The present disclosure relates to a power converter configured for limiting switching overvoltage. The power converter comprises a bottom commutation cell that includes a bottom power electronic switch and a bottom compensation circuit connected to a bottom parasitic inductance. The bottom compensation circuit applies a sample of the voltage induced across the bottom parasitic inductance at turn-off of the bottom power electronic switch to the reference node of the bottom gate driver. The power converter also comprises a top commutation cell that includes top power electronic switch and a top compensation circuit connected to the bottom parasitic inductance. The top compensation circuit applies a sample of the voltage induced across the bottom parasitic emitter upon turn-off of the top power electronic switch to the reference node of the top gate driver.

Abstract: A physical topology for receiving top and bottom power electronic switches comprises a top collector trace connected to a positive voltage power supply tab and having a connection area for a collector of a top power electronic switch, a bottom emitter trace connected to a negative voltage power supply tab and having a connection area for an emitter of the bottom power electronic switch, and a middle trace connected to a load tab and having a connection area for an emitter of the top power electronic switch and a connection area for a collector of the bottom power electronic switch. Sampling points are provided on the traces for voltages on the emitters of the top and bottom power electronic switches, on the trace for voltage of the collector of the bottom power electronic switch, and on the negative voltage power supply tab. The topology defines parasitic inductances. Sample voltages can be supplied to gate driver references.

Abstract: The present topology for controlled power switch module is concerned with a module where the parasitic inductance of the emitter of the top power switch is optimized to allow the injection of a sample of the overvoltage across this parasitic inductance in the gate drive circuit of the top power switch as a feedback to slow down the slope of the falling gate voltage during an overvoltage that is above a predetermined value.

Abstract: The present disclosure relates to a compensation circuit for independently controlling turn-on and turn-off of a power electronic switch through a gate driver. The compensation circuit includes a circuit path sampling a first portion of a voltage induced across an inductance of the power electronic switch at turn-on. Another circuit path samples a second portion of the voltage induced across the inductance of the power electronic switch at turn-off. The compensation circuit further includes a gate driver reference connection configured to respectively supply the sampled portions of the voltage during turn-on and turn-off of the power electronic switch. A compensation circuit controlling a first power electronic switch in parallel with a second power electronic switch, a commutation cell and a power converter having a pair of parallel legs, in which each power electronic switch is provided with the compensation circuit, are also disclosed.

Abstract: A turn-off overvoltage limiting for IGBT is described herein. The injection of a sample of the overvoltage across the IGBT in the gate drive to slow down the slope of the gate voltage decrease only during the overvoltage above a predetermined value is described herein. Techniques to increase the parasitic inductance to allow the control to limit an overvoltage at turn off of the second IGBT are also described herein.

Abstract: A turn-off overvoltage limiting for IGBT is described herein. The injection of a sample of the overvoltage across the IGBT in the gate drive to slow down the slope of the gate voltage decrease only during the overvoltage above a predetermined value is described herein. Techniques to increase the parasitic inductance to allow the control to limit an overvoltage at turn off of the second IGBT are also described herein.

Abstract: The present disclosure relates to a compensation circuit for independently controlling turn-on and turn-off of a power electronic switch through a gate driver. The compensation circuit includes a circuit path sampling a first portion of a voltage induced across an inductance of the power electronic switch at turn-on. Another circuit path samples a second portion of the voltage induced across the inductance of the power electronic switch at turn-off. The compensation circuit further includes a gate driver reference connection configured to respectively supply the sampled portions of the voltage during turn-on and turn-off of the power electronic switch. A compensation circuit controlling a first power electronic switch in parallel with a second power electronic switch, a commutation cell and a power converter having a pair of parallel legs, in which each power electronic switch is provided with the compensation circuit, are also disclosed.

Abstract: The present disclosure relates to a commutation cell and to a compensation circuit for limiting overvoltage across the power electronic switch of the commutation cell and for limiting a recovery current in a freewheel diode of the commutation cell. The power electronic switch has a parasitic emitter inductance. A variable gain compensation circuit generates a feedback from a voltage generated across the parasitic inductance of the emitter of the power switch at turn-on or turn-off of the power electronic switch. The compensation circuit provides the feedback to a control of the power electronic switch to reduce the voltage generated on the parasitic emitter inductance. A power converter including the commutation cell with the compensation circuit is also disclosed.

Abstract: The present topology for controlled power switch module is concerned with a module where the parasitic inductance of the emitter of the top power switch is optimized to allow the injection of a sample of the overvoltage across this parasitic inductance in the gate drive circuit of the top power switch as a feedback to slow down the slope of the falling gate voltage during an overvoltage that is above a predetermined value.