Patents by Inventor Maayan Suliman

Maayan Suliman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11842069
    Abstract: A storage system allocates single-level cell (SLC) blocks in its memory to act as a write buffer. A host sends the storage system a threshold indicating an amount of data that should be stored in the write buffer before the storage system flushes the write buffer to multi-level cell (MLC) blocks in the memory. Using this threshold can extend the amount of time that data is maintained in the write buffer, which can reduce the write-amplification factor and power consumption, as well as increase read performance of the data.
    Type: Grant
    Filed: February 4, 2022
    Date of Patent: December 12, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Einav Zilberstein, Hadas Oshinsky, Maayan Suliman
  • Patent number: 11809736
    Abstract: A storage system determines a memory fragmentation level for each of a plurality of logical block address ranges. The memory fragmentation level for a given logical block address range is determined according to the number of memory senses required to read that logical block address range in its current state of fragmentation and the number of memory senses required to read that logical block address range assuming no fragmentation. The memory fragmentation level correlates to the sequential read performance for that logical block address range in that an increase in the memory fragmentation level results in a decrease in sequential read performance.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: November 7, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Einav Zilberstein, Hadas Oshinsky, Maayan Suliman, Karin Inbar
  • Publication number: 20230229347
    Abstract: A storage system allocates single-level cell (SLC) blocks in its memory to act as a write buffer. A host sends the storage system a threshold indicating an amount of data that should be stored in the write buffer before the storage system flushes the write buffer to multi-level cell (MLC) blocks in the memory. Using this threshold can extend the amount of time that data is maintained in the write buffer, which can reduce the write-amplification factor and power consumption, as well as increase read performance of the data.
    Type: Application
    Filed: February 4, 2022
    Publication date: July 20, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Einav Zilberstein, Hadas Oshinsky, Maayan Suliman
  • Publication number: 20230195353
    Abstract: A storage system determines a memory fragmentation level for each of a plurality of logical block address ranges. The memory fragmentation level for a given logical block address range is determined according to the number of memory senses required to read that logical block address range in its current state of fragmentation and the number of memory senses required to read that logical block address range assuming no fragmentation. The memory fragmentation level correlates to the sequential read performance for that logical block address range in that an increase in the memory fragmentation level results in a decrease in sequential read performance.
    Type: Application
    Filed: December 21, 2021
    Publication date: June 22, 2023
    Applicant: Western Digital Technologies, Inc.
    Inventors: Einav Zilberstein, Hadas Oshinsky, Maayan Suliman, Karin Inbar