Patents by Inventor Machio Yamagishi
Machio Yamagishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7304696Abstract: The present invention is an image display apparatus having pixels PXLs arranged in a matrix form, and comprises a display panel displaying images by reflecting external light from the front side or by having illumination light from the back side transmit therethrough, and a flat-type back light arranged at the back of the display panel and radiating the illumination light. Each pixel PXL is divided on a flat surface into a reflection area R for reflecting the external light incident from the front side of the display panel to display an image and a transmission area T for transmitting the illumination light incident from the back side of the display panel to display an image.Type: GrantFiled: December 25, 2001Date of Patent: December 4, 2007Assignee: Sony CorporationInventor: Machio Yamagishi
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Patent number: 6969291Abstract: A display apparatus includes a substrate, a plurality of pixels formed on the substrate, and a barrier plate for separating adjoining pixels from each other. Each pixel includes a lower layer portion having wiring formed on the substrate, an upper layer portion having an organic electro-luminescent element, and a middle layer portion for insulating the lower layer portion and the upper layer portion from each other electrically. The organic electro-luminescent element is connected with the windings through a contact hole formed in the middle layer portion. The barrier plate is disposed in the upper layer portion so as to overlap with a region including a contact hole not suitable for forming the organic electro-luminescent element.Type: GrantFiled: June 30, 2003Date of Patent: November 29, 2005Assignee: Sony CorporationInventors: Tetsuo Urabe, Tatsuya Sasaoka, Mitsunobu Sekiya, Machio Yamagishi
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Publication number: 20040090175Abstract: A display apparatus includes a substrate, a plurality of pixels formed on the substrate, and a barrier plate for separating adjoining pixels from each other. Each pixel includes a lower layer portion having wiring formed on the substrate, an upper layer portion having an organic electro-luminescent element, and a middle layer portion for insulating the lower layer portion and the upper layer portion from each other electrically. The organic electro-luminescent element is connected with the windings through a contact hole formed in the middle layer portion. The barrier plate is disposed in the upper layer portion so as to overlap with a region including a contact hole not suitable for forming the organic electro-luminescent element.Type: ApplicationFiled: June 30, 2003Publication date: May 13, 2004Inventors: Tetsuo Urabe, Tatsuya Sasaoka, Mitsunobu Sekiya, Machio Yamagishi
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Patent number: 6614174Abstract: A display apparatus includes a substrate, a plurality of pixels formed on the substrate, and a barrier plate for separating adjoining pixels from each other. Each pixel includes a lower layer portion having wiring formed on the substrate, an upper layer portion having an organic electro-luminescent element, and a middle layer portion for insulating the lower layer portion and the upper layer portion from each other electrically. The organic electro-luminescent element is connected with the wiring through a contact hole formed in the middle layer portion. The barrier plate is disposed in the upper layer portion so as to overlap with a region including a contact hole not suitable for forming the organic electro-luminescent element.Type: GrantFiled: November 15, 2000Date of Patent: September 2, 2003Assignee: Sony CorporationInventors: Tetsuo Urabe, Tatsuya Sasaoka, Mitsunobu Sekiya, Machio Yamagishi
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Publication number: 20030107688Abstract: The present invention is an image display apparatus having pixels PXLs arranged in a matrix form, and comprises a display panel displaying images by reflecting external light from the front side or by having illumination light from the back side transmit therethrough, and a flat-type back light arranged at the back of the display panel and radiating the illumination light. Each pixel PXL is divided on a flat surface into a reflection area R for reflecting the external light incident from the front side of the display panel to display an image and a transmission area T for transmitting the illumination light incident from the back side of the display panel to display an image.Type: ApplicationFiled: October 18, 2002Publication date: June 12, 2003Inventor: Machio Yamagishi
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Patent number: 6501466Abstract: Each of picture elements comprises an input transistor for accepting a signal current from a data line when a scanning line is selected, a conversion transistor for converting the signal current into a voltage and for holding thus converted voltage, and a drive transistor for driving a light emitting device with drive current corresponding to the converted voltage. The conversion transistor flows the signal current to its channel to generate the voltage corresponding to the converted voltage and a capacitor to restrain the generated voltage. Further the drive transistor flows the drive current corresponding to the voltage stored in the capacitor. In this case the threshold voltage of the drive transistor is set not to be smaller than the threshold voltage of the conversion transistor, and thereby a leakage current flowing through the light emitting device is suppressed.Type: GrantFiled: November 13, 2000Date of Patent: December 31, 2002Assignee: Sony CorporationInventors: Machio Yamagishi, Akira Yumoto
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Patent number: 6054366Abstract: In order to avoid any concentration of an electric field to gate edges of a two-layered structure and to improve an accumulation performance of charge, a semiconductor device includes a semiconductor substrate; an element isolation region formed to define an element formation region in the semiconductor substrate; a first gate insulating layer formed in a part of a surface of the element formation region; a first gate electrode formed on the first gate insulating layer; an insulating layer for surrounding the first gate electrode with a top surface of the insulating layer being substantially in the same plane as that of a top surface of the first electrode; a second gate insulating layer formed on the first gate electrode; and a second gate electrode formed on the second gate insulating layer. Also, a method therefor is provided.Type: GrantFiled: March 2, 1998Date of Patent: April 25, 2000Assignee: Sony CorporationInventors: Machio Yamagishi, Takashi Shimada
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Patent number: 5808339Abstract: In order to avoid any concentration of an electric field to gate edges of a two-layered structure and to improve an accumulation performance of charge, a semiconductor device includes a semiconductor substrate; an element isolation region formed to define an element formation region in the semiconductor substrate; a first gate insulating layer formed in a part of a surface of the element formation region; a first gate electrode formed on the first gate insulating layer; an insulating layer for surrounding the first gate electrode with a top surface of the insulating layer being substantially in the same plane as that of a top surface of the first electrode; a second gate insulating layer formed on the first gate electrode; and a second gate electrode formed on the second gate insulating layer. Also, a method therefor is provided.Type: GrantFiled: June 10, 1997Date of Patent: September 15, 1998Assignee: Sony CorporationInventors: Machio Yamagishi, Takashi Shimada
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Patent number: 5768184Abstract: A non-volatile semiconductor memory device including a plurality of non-volatile memory cells and a plurality of reference cells provided for corresponding to storage states in the non-volatile memory cell, generating a reference current which is a current between two output currents of at least two reference cells or a current proportional to the current when data reading from the non-volatile memory cell, and comparing the reference current and a current from the non-volatile memory cell to read out a data stored in the non-volatile memory cell.Type: GrantFiled: January 31, 1996Date of Patent: June 16, 1998Assignee: Sony CorporationInventors: Yutaka Hayashi, Machio Yamagishi
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Patent number: 5737281Abstract: An ultraviolet laser beam emitted from a laser beam source 1 is subjected to on/off control at an AOM 3, is linearly scanned at an equal speed by a polygon mirror 5 and an f.THETA. lens 6, is collected by an object lens 7, and is selectively spot-irradiated to a memory cell array of a semiconductor chip 8 on an XY stage 9 two-dimensionally moved by a control device 10 so as to write a pattern corresponding to desired data, whereby a custom ROM can be supplied in flexible production on a timely basis meeting market trends.Type: GrantFiled: March 5, 1996Date of Patent: April 7, 1998Assignee: Sony CorporationInventors: Minoru Takeda, Yutaka Hayashi, Machio Yamagishi
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Patent number: 5627781Abstract: A rewritable nonvolatile semiconductor memory device having a plurality of memory cells which are electrically and reversably variable in threshold values and one pair of reference cells, provided for each predetermined number of memory cells, having the same cross-sectional structure as the memory cells, the pair of reference cells having written in them data of opposite phases, and, at the time of reading, the currents of the pair of reference cells being combined to produce a reference current and the data being determined by comparing this with the signal current of the memory cell.Type: GrantFiled: November 8, 1995Date of Patent: May 6, 1997Assignee: Sony CorporationInventors: Yutaka Hayashi, Machio Yamagishi
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Patent number: 5437762Abstract: The invention concerns a method of forming various kinds of SOI structures and semiconductor memory devices using the forming technique. It is useful, for example, in SRAM or EEPROM devices. In EEPROM, it relates, in particular, to a method of manufacturing a non-volatile memory device in which a control gate electrode layer is laminated by way of an insulator film on a floating gate electrode layer. It includes a method of manufacturing a structure via the steps of forming an etching stopping layer on the surface of a silicon substrate, forming an epitaxially grown silicon layer on said etching stopping layer, bonding said silicon substrate formed with said silicon layer with another substrate as the insulator substrate, grinding said silicon substrate from the rear face and etching it until said etching stopping layer is exposed and removing said etching stopper layer, with or without polishing the other surface of said silicon substrate.Type: GrantFiled: July 13, 1994Date of Patent: August 1, 1995Assignee: Siemens AktiengesellschaftInventors: Akihiko Ochiai, Makoto Hashimoto, Takeshi Matsushita, Machio Yamagishi, Hiroshi Sato, Muneharu Shimanoe