Patents by Inventor Maciej Bajkowski
Maciej Bajkowski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11860737Abstract: An interface software layer is interposed between at least one application and a plurality of coprocessors. A data and command stream issued by the application(s) to an API of an intended one of the coprocessors is intercepted by the layer, which also acquires and stores the execution state information for the intended coprocessor at a coprocessor synchronization boundary. At least a portion of the intercepted data and command stream data is stored in a replay log associated with the intended coprocessor. The replay log associated with the intended coprocessor is then read out, along with the stored execution state information, and is submitted to and serviced by at least one different one of the coprocessors other than the intended coprocessor.Type: GrantFiled: March 16, 2019Date of Patent: January 2, 2024Assignee: VMware, Inc.Inventors: Mazhar Memon, Subramanian Rama, Maciej Bajkowski
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Patent number: 11748152Abstract: In a data processing system running at least one application on a hardware platform that includes at least one processor and a plurality of coprocessors, at least one kernel dispatched by an application is intercepted by an intermediate software layer running logically between the application and the system software. Compute functions are determined within kernel(s), and data dependencies are determined among the compute functions. The compute functions are dispatched to selected ones of the coprocessors based at least in part on the determined data dependencies and kernel results are returned to the application that dispatched the respective kernel.Type: GrantFiled: October 18, 2021Date of Patent: September 5, 2023Inventors: Mazhar Memon, Subramanian Rama, Maciej Bajkowski
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Publication number: 20220035654Abstract: In a data processing system running at least one application on a hardware platform that includes at least one processor and a plurality of coprocessors, at least one kernel dispatched by an application is intercepted by an intermediate software layer running logically between the application and the system software. Compute functions are determined within kernel(s), and data dependencies are determined among the compute functions. The compute functions are dispatched to selected ones of the coprocessors based at least in part on the determined data dependencies and kernel results are returned to the application that dispatched the respective kernel.Type: ApplicationFiled: October 18, 2021Publication date: February 3, 2022Inventors: Mazhar MEMON, Subramanian RAMA, Maciej BAJKOWSKI
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Patent number: 11169843Abstract: In a data processing system running at least one application on a hardware platform that includes at least one processor and a plurality of coprocessors, at least one kernel dispatched by an application is intercepted by an intermediate software layer running logically between the application and the system software. Compute functions are determined within kernel(s), and data dependencies are determined among the compute functions. The compute functions are dispatched to selected ones of the coprocessors based at least in part on the determined data dependencies and kernel results are returned to the application that dispatched the respective kernel.Type: GrantFiled: January 8, 2020Date of Patent: November 9, 2021Assignee: VMWARE, INC.Inventors: Mazhar Memon, Subramanian Rama, Maciej Bajkowski
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Publication number: 20200257553Abstract: In a data processing system running at least one application on a hardware platform that includes at least one processor and a plurality of coprocessors, at least one kernel dispatched by an application is intercepted by an intermediate software layer running logically between the application and the system software. Compute functions are determined within kernel(s), and data dependencies are determined among the compute functions. The compute functions are dispatched to selected ones of the coprocessors based at least in part on the determined data dependencies and kernel results are returned to the application that dispatched the respective kernel.Type: ApplicationFiled: January 8, 2020Publication date: August 13, 2020Inventors: Mazhar MEMON, Subramanian RAMA, Maciej BAJKOWSKI
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Patent number: 10534639Abstract: In a data processing system running at least one application on a hardware platform that includes at least one processor and a plurality of coprocessors, at least one kernel dispatched by an application is intercepted by an intermediate software layer running logically between the application and the system software. Compute functions are determined within kernel(s), and data dependencies are determined among the compute functions. The compute functions are dispatched to selected ones of the coprocessors based at least in part on the determined data dependencies and kernel results are returned to the application that dispatched the respective kernel.Type: GrantFiled: July 6, 2017Date of Patent: January 14, 2020Assignee: Bitfusion.io, Inc.Inventors: Mazhar Memon, Subramanian Rama, Maciej Bajkowski
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Publication number: 20190213062Abstract: An interface software layer is interposed between at least one application and a plurality of coprocessors. A data and command stream issued by the application(s) to an API of an intended one of the coprocessors is intercepted by the layer, which also acquires and stores the execution state information for the intended coprocessor at a coprocessor synchronization boundary. At least a portion of the intercepted data and command stream data is stored in a replay log associated with the intended coprocessor. The replay log associated with the intended coprocessor is then read out, along with the stored execution state information, and is submitted to and serviced by at least one different one of the coprocessors other than the intended coprocessor.Type: ApplicationFiled: March 16, 2019Publication date: July 11, 2019Applicant: Bitfusion.io, Inc.Inventors: Mazhar MEMON, Subramanian RAMA, Maciej BAJKOWSKI
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Patent number: 10261847Abstract: An interface software layer is interposed between at least one application and a plurality of coprocessors. A data and command stream issued by the application(s) to an API of an intended one of the coprocessors is intercepted by the layer, which also acquires and stores the execution state information for the intended coprocessor at a coprocessor synchronization boundary. At least a portion of the intercepted data and command stream data is stored in a replay log associated with the intended coprocessor. The replay log associated with the intended coprocessor is then read out, along with the stored execution state information, and is submitted to and serviced by at least one different one of the coprocessors other than the intended coprocessor.Type: GrantFiled: March 7, 2017Date of Patent: April 16, 2019Assignee: Bitfusion.io, Inc.Inventors: Mazhar Memon, Subramanian Rama, Maciej Bajkowski
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Publication number: 20190012197Abstract: In a data processing system running at least one application on a hardware platform that includes at least one processor and a plurality of coprocessors, at least one kernel dispatched by an application is intercepted by an intermediate software layer running logically between the application and the system software. Compute functions are determined within kernel(s), and data dependencies are determined among the compute functions. The compute functions are dispatched to selected ones of the coprocessors based at least in part on the determined data dependencies and kernel results are returned to the application that dispatched the respective kernel.Type: ApplicationFiled: July 6, 2017Publication date: January 10, 2019Applicant: Bitfusion.io, Inc.Inventors: Mazhar MEMON, Subramanian RAMA, Maciej BAJKOWSKI
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Publication number: 20170293510Abstract: An interface software layer is interposed between at least one application and a plurality of coprocessors. A data and command stream issued by the application(s) to an API of an intended one of the coprocessors is intercepted by the layer, which also acquires and stores the execution state information for the intended coprocessor at a coprocessor synchronization boundary. At least a portion of the intercepted data and command stream data is stored in a replay log associated with the intended coprocessor. The replay log associated with the intended coprocessor is then read out, along with the stored execution state information, and is submitted to and serviced by at least one different one of the coprocessors other than the intended coprocessor.Type: ApplicationFiled: March 7, 2017Publication date: October 12, 2017Applicant: Bitfusion.io, Inc.Inventors: Mazhar MEMON, Subramanian RAMA, Maciej BAJKOWSKI
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Patent number: 9502119Abstract: According to one general aspect, an apparatus may include a plurality of voltage boosted circuits. Each voltage boosted circuit may include a power gater configured to select between an array supply voltage and a second voltage, wherein the second supply voltage is greater than the array supply voltage. Each voltage boosted circuit may include may also include a distributed boost capacitor configured to generate, in part, the second supply voltage. Each distributed boost capacitor may be physically located throughout a boosting network. Each voltage boosted circuit may further include a driver configured to generate an electrical signal based upon, as selected by the power-gater, either the array supply voltage or the second supply voltage.Type: GrantFiled: July 29, 2015Date of Patent: November 22, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Maciej Bajkowski, Jan-Michael Huber, Ravi Venkatesa
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Publication number: 20160148659Abstract: According to one general aspect, an apparatus may include a plurality of voltage boosted circuits. Each voltage boosted circuit may include a power gater configured to select between an array supply voltage and a second voltage, wherein the second supply voltage is greater than the array supply voltage. Each voltage boosted circuit may include may also include a distributed boost capacitor configured to generate, in part, the second supply voltage. Each distributed boost capacitor may be physically located throughout a boosting network. Each voltage boosted circuit may further include a driver configured to generate an electrical signal based upon, as selected by the power-gater, either the array supply voltage or the second supply voltage.Type: ApplicationFiled: July 29, 2015Publication date: May 26, 2016Inventors: Maciej BAJKOWSKI, Jan-Michael HUBER, Ravi VENKATESA
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Patent number: 9269409Abstract: Methods and systems to provide bit cell write-assist, including equalization of voltages of Bit and Bit nodes of a bit cell prior to a write operation. Equalization may be performed with a pulse-controlled transistor to transfer charge between the storage nodes. Pulse width and/or amplitude may be configurable, such as to scale with voltage. Bit cell write-assist may include reduction of bit cell retention strength during equalization, which may be continued during a write operation. Write-assist may be provided to each of multiple bit cells when a write operation is directed to a subset of the bit cells, which may conserve power and/or area. A partially-decoded address may be used to provide write-assistance to multiple bit cells prior to a write operation. Write-assistance may permit writing of Bit and Bit with a voltage swing significantly lower than an operating voltage of the bit cell.Type: GrantFiled: October 18, 2011Date of Patent: February 23, 2016Assignee: Intel CorporationInventors: Maciej Bajkowski, Giao N. Pham, Novat S. Nintunze, Hung C. Ngo
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Publication number: 20130268737Abstract: Methods and systems to provide bit cell write-assist, including equalization of voltages of Bit and Bit nodes of a bit cell prior to a write operation. Equalization may be performed with a pulse-controlled transistor to transfer charge between the storage nodes. Pulse width and/or amplitude may be configurable, such as to scale with voltage. Bit cell write-assist may include reduction of bit cell retention strength during equalization, which may be continued during a write operation. Write-assist may be provided to each of multiple bit cells when a write operation is directed to a subset of the bit cells, which may conserve power and/or area. A partially-decoded address may be used to provide write-assistance to multiple bit cells prior to a write operation. Write-assistance may permit writing of Bit and Bit with a voltage swing significantly lower than an operating voltage of the bit cell.Type: ApplicationFiled: October 18, 2011Publication date: October 10, 2013Inventors: Maciej Bajkowski, Giao N. Pham, Novat S. Nintunze, Hung C. Ngo
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Patent number: 8487657Abstract: A dynamic logic circuit includes an N channel transistor stack between a dynamic node and a first power supply terminal for receiving a plurality of logic signals. A P channel clock transistor is coupled between a second power supply terminal and the dynamic node is for receiving a clock signal. An N channel clock transistor is in series with the N channel stack and is between the dynamic node and the first power supply terminal is for receiving the clock signal. A keeper transistor has a first current electrode coupled to the dynamic node, a second current electrode coupled to a second power supply terminal, and a control electrode. A static logic circuit has an output for providing an output responsive to a state of the logic signals. The output is coupled to the control electrode of the keeper transistor.Type: GrantFiled: May 31, 2012Date of Patent: July 16, 2013Assignee: Freescale Semiconductor, Inc.Inventors: George P. Hoekstra, Ravindraraj Ramaraju, Maciej Bajkowski
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Patent number: 7499342Abstract: A dynamic module output device and methods thereof are disclosed. The dynamic module output device is connected to a dynamic module. The dynamic module output device provides the output of the dynamic module via two pathways. The first pathway is a direct output from the dynamic module. The second pathway includes a latch that stores the output of the dynamic module. The two output pathways are connected to a logic gate connected to downstream circuitry. Accordingly, data is provided to downstream circuitry rapidly via the first pathway, while being latched to allow the data to be available to the downstream circuitry after the evaluation phase. Such a parallel latching configuration provides enhanced efficiency in transfer and processing of information, especially in conjunction with utilization of precharge and evaluation phases.Type: GrantFiled: January 5, 2007Date of Patent: March 3, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Maciej Bajkowski, Ravindraraj Ramaraju, Andrew Russell
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Publication number: 20080279029Abstract: A data path of a memory is from an array of the memory, through a sense amplifier, through NOR gates, through N channel transistors, and through a latch that provides an output. The sense amplifier provides complementary data to the NOR gates which provide an output to the N channel transistors. The NOR gates provide outputs to the latch. This has the affect of providing outputs to gates of one inverter and drains of another inverter. Additional P channel transistors are in series with the inverters of the latch. The P channel transistor that is in series with the inverters whose drains are receiving the signal is made to be nonconductive by the output of the NOR gate to block current flow to the N channel transistor that is providing the input to the latch. The blocking of the current reduces the amount of current that the N channel transistor has to sink. This enables the N channel transistor, even at a reduced voltage, to be sufficiently conductive to flip the state of the latch.Type: ApplicationFiled: May 9, 2007Publication date: November 13, 2008Inventors: Maciej Bajkowski, Hamed Ghassemi, Huy B. Nguyen
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Patent number: 7450454Abstract: A data path of a memory is from an array of the memory, through a sense amplifier, through NOR gates, through N channel transistors, and through a latch that provides an output. The sense amplifier provides complementary data to the NOR gates which provide an output to the N channel transistors. The NOR gates provide outputs to the latch. This has the affect of providing outputs to gates of one inverter and drains of another inverter. Additional P channel transistors are in series with the inverters of the latch. The P channel transistor that is in series with the inverters whose drains are receiving the signal is made to be nonconductive by the output of the NOR gate to block current flow to the N channel transistor that is providing the input to the latch. The blocking of the current reduces the amount of current that the N channel transistor has to sink. This enables the N channel transistor, even at a reduced voltage, to be sufficiently conductive to flip the state of the latch.Type: GrantFiled: May 9, 2007Date of Patent: November 11, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Maciej Bajkowski, Hamed Ghassemi, Huy B. Nguyen
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Patent number: 7443223Abstract: A level shifting circuit having a signal input that operates in a first voltage domain and a signal output that operates in a second voltage domain. In some embodiments, the level shifting circuit includes a clocked level shifter. In some embodiments, the level shifting circuit includes a level shifting latch that latches a translated output signal. In one example, the level shifting latch includes a latch portion and a stack of transistors with a transistor having a control electrode coupled to a clock input.Type: GrantFiled: August 31, 2006Date of Patent: October 28, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Maciej Bajkowski, George P. Hoekstra, Hamed Ghassemi
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Publication number: 20080165590Abstract: A dynamic module output device and methods thereof are disclosed. The dynamic module output device is connected to a dynamic module. The dynamic module output device provides the output of the dynamic module via two pathways. The first pathway is a direct output from the dynamic module. The second pathway includes a latch that stores the output of the dynamic module. The two output pathways are connected to a logic gate connected to downstream circuitry. Accordingly, data is provided to downstream circuitry rapidly via the first pathway, while being latched to allow the data to be available to the downstream circuitry after the evaluation phase. Such a parallel latching configuration provides enhanced efficiency in transfer and processing of information, especially in conjunction with utilization of precharge and evaluation phases.Type: ApplicationFiled: January 5, 2007Publication date: July 10, 2008Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Maciej Bajkowski, Ravindraraj Ramaraju, Andrew Russell