Abstract: A power semiconductor module includes a power semiconductor die attached to the first metallized side, a passive component attached to the first metallized side, a first isolation layer encapsulating the power semiconductor die and the passive component, a first structured metallization layer on the first isolation layer, and a first plurality of electrically conductive vias extending through the first isolation layer from the first structured metallization layer to the power semiconductor die and the passive component.

Abstract: A power semiconductor module includes a power semiconductor die attached to the first metallized side, a passive component attached to the first metallized side, a first isolation layer encapsulating the power semiconductor die and the passive component, a first structured metallization layer on the first isolation layer, and a first plurality of electrically conductive vias extending through the first isolation layer from the first structured metallization layer to the power semiconductor die and the passive component.

Abstract: A semiconductor package includes a first semiconductor module including a plurality of semiconductor transistor chips and a first encapsulation layer disposed above the semiconductor transistor chips, and a second semiconductor module disposed above the first semiconductor module. The second semiconductor module includes a plurality of semiconductor driver channels and a second encapsulation layer disposed above the semiconductor driver channels. The semiconductor driver channels are configured to drive the semiconductor transistor chips.

Abstract: A power semiconductor module includes a direct copper bonded (DCB) substrate having a ceramic substrate, a first copper metallization bonded to a first main surface of the ceramic substrate and a second copper metallization bonded to a second main surface of the ceramic substrate opposite the first main surface. The power semiconductor module further includes a power semiconductor die attached the first copper metallization, a passive component attached the first copper metallization, a first isolation layer encapsulating the power semiconductor die and the passive component, a first structured metallization layer on the first isolation layer, and a first plurality of electrically conductive vias extending through the first isolation layer from the first structured metallization layer to the power semiconductor die and the passive component. An integrated power module and a method of manufacturing the integrated power module are also provided.

Abstract: A printed circuit board (PCB) has a first, structured metalization arranged on its top side and at least one second metalization arranged below the first metalization in a vertical direction, parallel to the first metalization and insulated therefrom. Also on the PCB top side is a bare semiconductor chip having contact electrodes connected by bonding wires to corresponding contact pads of the first metalization on the PCB top side. A first portion of the contact electrodes and corresponding contact pads carry high voltage during operation. All high-voltage-carrying contact pads are conductively connected to the second metalization via plated-through holes. An insulation layer completely covers the chip and a delimited region of the PCB around the chip, and all high-voltage-carrying contact pads and the plated-through holes are completely covered by the insulation layer. A second portion of the contact electrodes and corresponding contact pads are under low voltages during operation.

Abstract: Various embodiments provide a method of forming a bondpad, wherein the method comprises providing a raw bondpad, and forming a recess structure at a contact surface of the raw bondpad, wherein the recess structure comprises sidewalls being inclined with respect to the contact surface.

Abstract: An electronic device may comprise a semiconductor element and a wire bond connecting the semiconductor element to a substrate. Using a woven bonding wire may improve the mechanical and electrical properties of the wire bond. Furthermore, there may be a cost benefit. Woven bonding wires may be used in any electronic device, for example in power devices or integrated logic devices.

Abstract: Various embodiments provide a method of forming a bondpad, wherein the method comprises providing a raw bondpad, and forming a recess structure at a contact surface of the raw bondpad, wherein the recess structure comprises sidewalls being inclined with respect to the contact surface.

Abstract: A power semiconductor module includes a direct copper bonded (DCB) substrate having a ceramic substrate, a first copper metallization bonded to a first main surface of the ceramic substrate and a second copper metallization bonded to a second main surface of the ceramic substrate opposite the first main surface. The power semiconductor module further includes a power semiconductor die attached the first copper metallization, a passive component attached the first copper metallization, a first isolation layer encapsulating the power semiconductor die and the passive component, a first structured metallization layer on the first isolation layer, and a first plurality of electrically conductive vias extending through the first isolation layer from the first structured metallization layer to the power semiconductor die and the passive component. An integrated power module and a method of manufacturing the integrated power module are also provided.

Abstract: A semiconductor package includes a mold body having a first main face, a second main face opposite to the first main face and side faces connecting the first and second main faces, a first semiconductor module including a plurality of first semiconductor chips and a first encapsulation layer disposed above the first semiconductor chips, and a second semiconductor module disposed above the first semiconductor module. The second semiconductor module includes a plurality of second semiconductor channels and a second encapsulation layer disposed above the second semiconductor channels. The semiconductor package further includes a plurality of external connectors extending through one or more of the side faces of the mold body.

Abstract: A semiconductor package includes a first semiconductor module including a plurality of semiconductor transistor chips and a first encapsulation layer disposed above the semiconductor transistor chips, and a second semiconductor module disposed above the first semiconductor module. The second semiconductor module includes a plurality of semiconductor driver channels and a second encapsulation layer disposed above the semiconductor driver channels. The semiconductor driver channels are configured to drive the semiconductor transistor chips.

Abstract: A semiconductor package includes a mold body having a first main face, a second main face opposite to the first main face and side faces connecting the first and second main faces, a first semiconductor module including a plurality of first semiconductor chips and a first encapsulation layer disposed above the first semiconductor chips, and a second semiconductor module disposed above the first semiconductor module. The second semiconductor module includes a plurality of second semiconductor channels and a second encapsulation layer disposed above the second semiconductor channels. The semiconductor package further includes a plurality of external connectors extending through one or more of the side faces of the mold body.

Abstract: An electronic device may comprise a semiconductor element and a wire bond connecting the semiconductor element to a substrate. Using a woven bonding wire may improve the mechanical and electrical properties of the wire bond. Furthermore, there may be a cost benefit. Woven bonding wires may be used in any electronic device, for example in power devices or integrated logic devices.

Abstract: A printed circuit board (PCB) has a first, structured metalization arranged on its top side and at least one second metalization arranged below the first metalization in a vertical direction, parallel to the first metalization and insulated therefrom. Also on the PCB top side is a bare semiconductor chip having contact electrodes connected by bonding wires to corresponding contact pads of the first metalization on the PCB top side. A first portion of the contact electrodes and corresponding contact pads carry high voltage during operation. All high-voltage-carrying contact pads are conductively connected to the second metalization via plated-through holes. An insulation layer completely covers the chip and a delimited region of the PCB around the chip, and all high-voltage-carrying contact pads and the plated-through holes are completely covered by the insulation layer. A second portion of the contact electrodes and corresponding contact pads are under low voltages during operation.