Abstract: A camera device comprises an assembly having a first component and a second component which are connected to each other with a hollow holding member and a threaded fastener. The first component has a first socket with a first socket opening and a threaded bore extending from a bottom surface of the first socket. The second component has a second socket with a second socket opening, wherein the first socket opening and the second socket opening are configured to face each other when the first and second component are connected to each other. The first and second sockets each have threaded bores. A threaded fastener is configured to extend from the second component to the threaded bore of the first socket of the first component for engagement with the threaded bore such that the connection between the first and second components is secured.

Abstract: A system and a method include one or more control units including one or more processors configured to: receive a compiled ruleset including rules, receive a plan for a trip for one or more vehicles, determine if the rules are applicable to the plan, and discard each of the plurality of rules that is not applicable to the plan.

Abstract: The present disclosure provides a multilevel combinatorial optimizer for resource planning that identifies resource use preferences for a set of resources and a set of tasks to be performed; assigns resources to tasks to generate a strict-priority assignment set; in response to reaching a process break: identifies a subset of resources below a specified priority level; assigns the subset to unassigned tasks until each task is fully assigned to provide a full-assignment assignment set; in response to completing assignments for the set of tasks: rectifying inversions in the full-assignment assignment set by: selecting a tuple size for swapping the resources among tasks; identifying tuples of assignments that include an inversion; swapping the assignments identified in the tuples to remove the inversion and update the full-assignment assignment set to a reduced-inversion assignment set; and in response to the reduced-inversion assignment set including no inversions, outputting the reduced-inversion assignment se

Abstract: A formal verification approach verifies data access and data propagation paths in a circuit design by proving the unreachability of path cover properties of the circuit design. A security path verification system receives an original circuit model of a circuit design, along with parameters identifying a first location within the circuit design that is a source of tainted data and a second location within the circuit design that is coupled to the first location. The security path verification system also receives a selection of portions of the circuit design to be excluded from the verification analysis. Using an abstracted version of the exclude portions, the security verification system generates a second circuit model of the circuit design for use in determining whether the tainted data can reach the second location from the first location within the circuit design.

Abstract: A formal verification approach verifies data access and data propagation paths in a circuit design by proving the unreachability of path cover properties of the circuit design. A security path verification system receives an original circuit model of a circuit design, along with parameters identifying a first location within the circuit design that is a source of tainted data and a second location within the circuit design that is coupled to the first location. The security path verification system also receives a selection of portions of the circuit design to be excluded from the verification analysis. Using an abstracted version of the exclude portions, the security verification system generates a second circuit model of the circuit design for use in determining whether the tainted data can reach the second location from the first location within the circuit design.

Abstract: A formal verification approach verifies data access and data propagation paths in a circuit design by proving the unreachability of path cover properties of the circuit design. A security path verification system receives an original circuit model of a circuit design, along with parameters identifying a first location within the circuit design that is a source of tainted data and a second location within the circuit design that is coupled to the first location. The security path verification system also receives a selection of portions of the circuit design to be excluded from the verification analysis. Using an abstracted version of the exclude portions, the security verification system generates a second circuit model of the circuit design for use in determining whether the tainted data can reach the second location from the first location within the circuit design.