Abstract: A Universal Serial Bus (USB) modem (14) in which reassembly and segmentation operations are performed outside of the host computer (12) is disclosed. A USB interface device (30) is coupled to a digital signal processor (DSP) (32) in the modem (14), and contains a shared memory (44) in which bulk endpoints (51) are established, at which received ATM cell payload data may be stored. An ATM receive controller (134) is provided in the USB interface device (30), which receives each ATM cell from the DSP (32) and interrogates the ATM cell header to determine which, if any, virtual connection the cell corresponds. The ATM receive controller (134) then forwards the payload portion of the ATM cell, but not the ATM cell header, to the endpoint (51) corresponding to the virtual connection to which the ATM cell is directed. The disclosed ATM receive controller (134) also includes logic (64) for calculating a cyclic redundancy check value over the payload portion of the ATM cells that make up an ATM packet.

Abstract: A Universal Serial Bus (USB) modem (14) in which reassembly and segmentation operations are performed outside of the host computer (12) is disclosed. A USB interface device (30) is coupled to a digital signal processor (DSP) (32) in the modem (14), and contains a shared memory (44) in which bulk endpoints (240) are established, at which ATM packet header and payload data are stored prior to transmission. An ATM transmit controller (132) retrieves the header portion of the ATM packet from a transmit endpoint (240) and stores the information in registers (252, 254, 256) in the ATM transmit controller (132). A four-byte ATM cell header is then transmitted to byte buffers (268) and to the DSP (32) for transmission over the communications facility. Afterwards, payload data is retrieved from the transmit endpoint (240) in shared memory (44), and forwarded to byte buffers (268) for transmission.

Abstract: A Universal Serial Bus (USB) modem (14) having two operating modes, namely Digital Subscriber Loop (DSL) mode and a voice-band mode, is disclosed. A USB interface device (30) is coupled to a digital signal processor (DSP) (32) and contains a shared memory (44) in which USB endpoints are established for data communication. In the DSL mode, an ATM receive controller (134) receives each ATM cell from the DSP (32) and interrogates the ATM cell header to determine the virtual connection to the corresponding cell, and then forwards the payload portion of the ATM cell, but not the ATM cell header. In the voice-band mode, the ATM receive controller (134) and ATM transmit controller (132) operate in a simple streaming mode. A host interface controller (135) is also provided, by way of which facsimile communications are carried out simultaneously with DSL communications, or in separate sessions relative to voice-band data communications.

Abstract: A USB function device (14) for coupling to a USB host (12). The USB function device (14), comprises circuitry (32) for providing a capability to the USB host, where the circuitry for the capability comprises an address space. The USB function device further comprises a USB interface circuit (136) coupled between the USB host (12) and the circuitry (32) for providing a capability to the USB host. The USB interface circuit comprises a memory area (106) comprising a code overlay endpoint (1061) accessible to the USB host for writing two or more code blocks to the code overlay endpoint. The USB interface circuit further comprises circuitry (150-163) for communicating a first of the code blocks from the code overlay endpoint to the address space and for subsequently communicating a second of the code blocks from the code overlay endpoint to the address space.

Abstract: A USB function device (14) for coupling to a USB host (12). The USB function device (14) comprises circuitry (32) for providing a capability to the USB host, where the circuitry for providing a capability comprises an address space (VBUS). The USB function device (14) further comprises a USB interface circuit (30) coupled between the USB host and the circuitry for providing a capability to the USB host. The USB interface circuit (30) comprises a memory area (44, 106) comprising a write endpoint (1062) accessible to the USB host for writing a plurality of bytes to the memory area via the write endpoint. The plurality of bytes comprise data information and protocol information. The write endpoint comprises an endpoint-type other than a control-type endpoint. The USB interface circuit also comprises circuitry for decoding (166) the protocol information and circuitry for communicating the data information to the address space in response to the protocol information.