Abstract: The present description concerns a system comprising at least one first and one second memory circuits; and a direct data transfer circuit which is adapted to receiving specific instructions originating from an external processor, and to decoding specific instructions comprising: a specific instruction SET_REGION of definition of a sub-region in the first memory circuit towards and from which the data will be transferred; and a specific instruction of transfer between said sub-region and the second memory circuit, the specific transfer instruction comprising a first address field containing the relative coordinates, in said sub-region, of a first reference cell.

Abstract: The present description concerns a memory device (200) comprising: a memory circuit (201) implementing operations and performing elementary operations including a reading, a writing, or a computing operation; a control circuit (205) receiving instructions from a processor (231), and breaking down each received instruction into a plurality of elementary operations to generate an elementary operation request flow; a circuit (203) of direct data transfer from or to said memory circuit (201), the transfer circuit (203) receiving instructions from the processor (231), breaking down each received instruction into a plurality of elementary operations to be performed in said memory circuit to generate an elementary operation request flow; an internal data exchange link (204) directly coupling said memory circuit (201) to the direct transfer circuit (203); and an arbitration circuit (309).

Abstract: The present description concerns a memory device (200) comprising: a memory circuit (201) implementing operations and performing elementary operations including a reading, a writing, or a computing operation; a control circuit (205) receiving instructions from a processor (231), and breaking down each received instruction into a plurality of elementary operations to generate an elementary operation request flow; a circuit (203) of direct data transfer from or to said memory circuit (201), the transfer circuit (203) receiving instructions from the processor (231), breaking down each received instruction into a plurality of elementary operations to be performed in said memory circuit to generate an elementary operation request flow; an internal data exchange link (204) directly coupling said memory circuit (201) to the direct transfer circuit (203); and an arbitration circuit (309).

Abstract: A computing device divides an area of a main memory wherein a data structure is saved into NbS1 subdivisions, and then the computing device computes a weight wS,NbS1(k) for each of the NbS1 subdivisions using the following relationship: wS,NbS1(k)=PS(1+(k?1)×(NbS0?1)/(NbS1?1)), where: k is the order number k of one of the NbS1 subdivisions, and PS( ) is a predetermined function that is continuous over an interval [1; NbS0] and defined over each interval [k0, k0+1] by a polynomial of order less than four, where k0 is an integer order number contained in the interval [1; NbS0], and then when a datum Dk,n contained in a subdivision k of the main memory has to be transferred to a secondary memory, the computing device transfers a block of wS,NbS1(k) data containing the datum Dk,n where wS,NbS1(k) is the weight computed for this subdivision k.

Abstract: A memory circuit including: a plurality of elementary storage cells arranged in an array of rows and of columns, the cells of a same column sharing a same read bit line and a same write bit line; an internal control circuit capable of implementing a calculation operation including the simultaneous activation in read mode of at least two rows of the array; and a shuffle circuit including a data input register, a configuration register, and an output port, the shuffle circuit being capable of delivering on its output port the data stored in its input register shuffled according to a shuffle operation defined according to the state of its configuration register.

Abstract: Method for constructing a signature characteristic of the accesses, by a microprocessor, to a memory wherein: each time the microprocessor executes an access instruction for accessing a datum of a data structure, the microprocessor retrieves the identifier of the data structure and a position identifier that identifies the position of the datum accessed inside this data structure, the temporally ordered series of the position identifiers thus retrieved forming a retrieved access pattern, then for each retrieved access pattern associated with one and the same data structure identifier, the microprocessor constructs a statistical distribution on the basis of just the position identifiers of this retrieved access pattern, the set of the statistical distributions thus constructed and associated with the identifier of this data structure forming the signature characteristic of the accesses to the memory.

Abstract: A memory circuit including: a plurality of elementary storage cells arranged in an array of rows and of columns; a data input/output port; an address input port; a mode selection input port; and an internal control circuit configured to: read a mode selection signal applied to the mode selection port; when the mode selection signal is in a first state, read an address of a row from the address input port and implement a read or write operation in this row; and when the mode selection signal is in a second state, read from the data input/output port an instruction signal and implement an operation including the simultaneous activation in read or write mode of at least two rows.

Abstract: A memory circuit including: a plurality of elementary storage cells arranged in an array of rows and of columns; a data input/output port; an address input port; a mode selection input port; and an internal control circuit configured to: read a mode selection signal applied to the mode selection port; when the mode selection signal is in a first state, read an address of a row from the address input port and implement a read or write operation in this row; and when the mode selection signal is in a second state, read from the data input/output port an instruction signal and implement an operation including the simultaneous activation in read or write mode of at least two rows.

Abstract: A memory circuit including: a plurality of elementary storage cells arranged in an array of rows and of columns, the cells of a same column sharing a same read bit line and a same write bit line; an internal control circuit capable of implementing a calculation operation including the simultaneous activation in read mode of at least two rows of the array; and a shuffle circuit including a data input register, a configuration register, and an output port, the shuffle circuit being capable of delivering on its output port the data stored in its input register shuffled according to a shuffle operation defined according to the state of its configuration register.

Abstract: A memory circuit including: a plurality of elementary storage cells arranged in an array of rows and of columns; a data input/output port; an address input port; a mode selection input port; and an internal control circuit configured to: read a mode selection signal applied to the mode selection port; when the mode selection signal is in a first state, read an address of a row from the address input port and implement a read or write operation in this row; and when the mode selection signal is in a second state, read from the data input/output port an instruction signal and implement an operation including the simultaneous activation in read or write mode of at least two rows.