Patents by Inventor Mahantesh D. Narwade

Mahantesh D. Narwade has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • GENERATING A REDUCED BLOCK MODEL VIEW ON-THE-FLY
    Publication number: 20220327266
    Abstract: A word-level design model may be loaded into memory. Next, a masking layer may be created which includes objects in the word-level design model that are not used by an IC design analysis system. The masking layer may then be used to provide a reduced block model view on-the-fly to the IC design analysis system.
    Type: Application
    Filed: March 23, 2022
    Publication date: October 13, 2022
    Applicant: Synopsys, Inc.
    Inventors: Mahantesh D. Narwade, Soumen Ghosh, Mark Roizman, Vijaya V. Varkey, Abhinav Singla, Rajarshi Mukherjee
  • Clock-domain-crossing specific design mutations to model silicon behavior and measure verification robustness
    Patent number: 9990453
    Abstract: Methods and apparatuses related to clock-domain-crossing (CDC) specific design mutations to model silicon behavior and measure verification robustness are described. CDC signal paths can be identified in a circuit design. Next, synchronization circuitry associated with the CDC signal paths can be identified. Design mutations can be added to the identified synchronization circuitry. The design mutations can then be used during functional verification to measure verification robustness of a circuit verification test suite.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: June 5, 2018
    Assignee: SYNOPSYS, INC.
    Inventors: Namit K. Gupta, Jean-Marc A. Forey, Mahantesh D. Narwade, Horia A. Toma
  • Accurate glitch detection
    Patent number: 9792394
    Abstract: Systems and techniques for detecting design problems in a circuit design are described. A higher-level abstraction of the circuit design can be synthesized to obtain a lower-level abstraction of the circuit design, and a mapping between signals in the higher-level abstraction and the signals in the lower-level abstraction. A design problem can be detected in the circuit design in response to determining that a possible glitch in a signal in the lower-level abstraction is not blocked when an enable signal is assigned a blocking value. The enable signal and the corresponding blocking value are identified by analyzing the higher-level abstraction.
    Type: Grant
    Filed: January 30, 2016
    Date of Patent: October 17, 2017
    Assignee: Synopsys, Inc.
    Inventors: Kaushik De, Dipti Ranjan Senapati, Mahantesh D. Narwade, Namit K. Gupta, Rajarshi Mukherjee
  • ACCURATE GLITCH DETECTION
    Publication number: 20170053051
    Abstract: Systems and techniques for detecting design problems in a circuit design are described. A higher-level abstraction of the circuit design can be synthesized to obtain a lower-level abstraction of the circuit design, and a mapping between signals in the higher-level abstraction and the signals in the lower-level abstraction. A design problem can be detected in the circuit design in response to determining that a possible glitch in a signal in the lower-level abstraction is not blocked when an enable signal is assigned a blocking value (the enable signal and the corresponding blocking value are identified by analyzing the higher-level abstraction).
    Type: Application
    Filed: January 30, 2016
    Publication date: February 23, 2017
    Applicant: Synopsys, Inc.
    Inventors: Kaushik De, Dipti Ranjan Senapati, Mahantesh D. Narwade, Namit K. Gupta, Rajarshi Mukherjee
  • CLOCK-DOMAIN-CROSSING SPECIFIC DESIGN MUTATIONS TO MODEL SILICON BEHAVIOR AND MEASURE VERIFICATION ROBUSTNESS
    Publication number: 20160292331
    Abstract: Methods and apparatuses related to clock-domain-crossing (CDC) specific design mutations to model silicon behavior and measure verification robustness are described. CDC signal paths can be identified in a circuit design. Next, synchronization circuitry associated with the CDC signal paths can be identified. Design mutations can be added to the identified synchronization circuitry. The design mutations can then be used during functional verification to measure verification robustness of a circuit verification test suite.
    Type: Application
    Filed: March 30, 2015
    Publication date: October 6, 2016
    Applicant: SYNOPSYS, INC.
    Inventors: Namit K. Gupta, Jean-Marc A. Forey, Mahantesh D. Narwade, Horia A. Toma