Abstract: An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A dithering circuit is coupled to the reference signal and injects a short sequence dither signal into the reference signal in order to overcome quantization noise and thereby improve RMS phase-error detection for integer channels.

Abstract: An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A dithering circuit is coupled to the reference signal and injects a short sequence dither signal into the reference signal in order to overcome quantization noise and thereby improve RMS phase-error detection for integer channels.

Abstract: An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A dithering circuit is coupled to the reference signal and injects a short sequence dither signal into the reference signal in order to overcome quantization noise and thereby improve RMS phase-error detection for integer channels.

Abstract: An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A dithering circuit is coupled to the reference signal and injects a short sequence dither signal into the reference signal in order to overcome quantization noise and thereby improve RMS phase-error detection for integer channels.

Abstract: An embodiment of the present invention provides a phase locked loop that operates on clock signals derived from an RF clock signal generated by the phase locked loop. A frequency reference input provides a reference clock. A controllable oscillator generates the RF clock signal. A phase detection circuit operates on the reference clock to provide digital phase error samples indicative of a phase difference between the reference clock and the RF clock. A dithering circuit is coupled to the reference signal and injects a short sequence dither signal into the reference signal in order to overcome quantization noise and thereby improve RMS phase-error detection for integer channels.

Abstract: Envelope limiting for a polar modulator. A system is provided that intelligently compresses the amplitude modulation in a polar modulator so that it can be implemented with a single-stage variable gain amplifier. Limiting the amplitude modulation range on the low side prevents collapse of the transmit signal's time-varying envelope and eases circuit implementation. Limiting the amplitude modulation range on the high side reduces the peak-to-average ratio of the waveform and thereby improves the efficiency of the radio transmitter.

Abstract: Envelope limiting for a polar modulator. A system is provided that intelligently compresses the amplitude modulation in a polar modulator so that it can be implemented with a single-stage variable gain amplifier. Limiting the amplitude modulation range on the low side prevents collapse of the transmit signal's time-varying envelope and eases circuit implementation. Limiting the amplitude modulation range on the high side reduces the peak-to-average ratio of the waveform and thereby improves the efficiency of the radio transmitter.

Abstract: Envelope limiting for a polar modulator. A system is provided that intelligently compresses the amplitude modulation in a polar modulator so that it can be implemented with a single-stage variable gain amplifier. Limiting the amplitude modulation range on the low side prevents collapse of the transmit signal's time-varying envelope and eases circuit implementation. Limiting the amplitude modulation range on the high side reduces the peak-to-average ratio of the waveform and thereby improves the efficiency of the radio transmitter.

Abstract: A non-coherent method for (PN) code synchronization and eliminates the need for prior clock synchronization between a transmitter and receiver. The method further eliminates any need for prior knowledge of a transmitted data sequence to provide synchronization. In the method, based on a coarse estimation of the carrier frequency, a received CDMA intermediate frequency (IF) signal is baseband converted to in-phase (I) and quadrature-phase (Q) components. The baseband I and Q components are then used to calculate an estimated delay {circumflex over (&tgr;)} at a PN synchronization roll-over point. The estimated delay {circumflex over (&tgr;)} is used in an intermediate data sequence in the synchronization roll-over calculation process to more accurately estimate carrier frequency error and phase offset for the IF carrier signal used in the baseband conversion process.