Abstract: Systems and modules for use in trellis-based decoding of encoded sets of data bits. A memory system has multiple arrays for storing an index for each one of multiple states. With each array element being associated with a state through which a decoding path may pass through, the contents of each array element is an index which points to an immediately preceding state. This immediately preceding state is represented by another array element in another array. Each array is populated with array element entries as encoded data set are received by a separate decoder which generates the indices. For every given number of arrays in a group, a trace-back process traces back the path followed by an encoding procedure for encoding the encoded set. By tracing back this path through the various arrays, the original unencoded set of data bits can be found.

Abstract: The present invention discloses an optimal hardware implementation of the FFT/IFFT operation that minimizes the number of clock cycles required to compute the FFT/IFFT while at the same time minimizing the number of complex multipliers needed. For performing an N-point FFT/IFFT operation in N clock cycles, the optimal hardware implementation consists of several modules. An input module receives a plurality of inputs in parallel and combines the inputs after applying a multiplication factor to each of the inputs. At least one multiplicand generator is used to provide multiplicands to the system. At least two complex multiplier modules for performing complex multiplications are required with at least one of the complex multiplier modules receiving an output from the input module. Each of the complex multiplier modules receives multiplicands from the at least one multiplicand generator. Furthermore, at least one of the complex multiplier modules receives an output of another complex multiplier module.

Abstract: Systems and modules for use in trellis-based decoding of convolutionally encoded sets of data bits. A first calculation module receives an encoded set of data bits and calculates a signal distance or a measure of the differences between the encoded set and each one of a group of predetermined states, each state being represented by a sequence of data bits. The first calculation module consists of multiple parallel calculation submodules with each submodule being tasked to perform an XOR operation between the encoded set and one of the predetermined states. Multiple parallel second calculation modules each multiple receiving the output of the first calculation module, calculates cumulative signal distances using the output of the first calculation module. Each second calculation module has multiple parallel addition submodules with each addition submodule receiving a specific cumulative signal distance and one of the signal distances calculated by the first calculation.

Abstract: Systems and modules for use in trellis-based decoding of encoded sets of data bits. A memory system has multiple arrays for storing an index for each one of multiple states. With each array element being associated with a state through which a decoding path may pass through, the contents of each array element is an index which points to an immediately preceding state. This immediately preceding state is represented by another array element in another array. Each array is populated with array element entries as encoded data set are received by a separate decoder which generates the indices. For every given number of arrays in a group, a trace-back process traces back the path followed by an encoding procedure for encoding the encoded set. By tracing back this path through the various arrays, the original unencoded set of data bits can be found.

Abstract: A method for computing an intermediate result in squaring a number using a multiplier circuit of predetermined operand size, the method including the steps of representing a number to be squared as a vector of binary digits; grouping the vector into successive segments each having a length of the predetermined operand size; multiplying a first segment value by a second segment value to generate a first product value; the second at least one of the segment values to derive a second product value; halving the second product value to generate a halved second product value; accumulating the first product value with the halved second product value to generate an accumulated value; and doubling the accumulated value to generate the intermediate result.

Abstract: A multiplier for computing a final product of a first operand and a second operand comprising a multiplier array for forming a product of the first operand and second operand in carry-save form; a carry-save adder for adding said carry-save partial products and an accumulatd sum to produce a carry and save values; a carry-lookahead adder for adding said carry and save values to produce a product value and a carry-out value; a general purpose adder for adding said carry-out and said product value to produce said final product.

Abstract: Systems, methods and devices for scrambling/descrambling sets of data bits using subsets of a recurring sequence of scrambler bits. A self-synchronous scrambler, regardless of the generating polynomial being implemented, will generate repeating sequences of scrambler bits regardless of the initial stage of the scrambler. To implement a parallel scrambler, given a current state of the scrambler, the next n states of the scrambler are predicted based on the current state of the scrambler. The scrambling operation can then be preformed using the values in the current state—parallel logic operations between preselected bits of the current state will yield the required values to be used in scrambling an incoming parallel data set. Once these required values are generated, a parallel logical operation between the required values and the incoming data set will result in the scrambled output data.

Abstract: Methods and devices for encoding in parallel a set of data bits for use in communications systems. The set of data bits to be encoded is divided into two subsets with the first subset being encoded in parallel using the second subset. The first subset is also encoded in parallel using the second subset. The first subset is also encoded in parallel using a subset of an immediately preceding set of data bits. Parallel encoding is realized by using an encoding module utilizing multiple single bit submodule. Each submodule receives a single bit from the first subset and either the second subset or the subset of the immediately preceding data set. Each single bit submodule produces a pair of output bits from the convolutional encoding of a single bit of the first subset and either the second subset of the subset of the immediately preceding data set. The multiple single bit submodules operate in parallel to simultaneously and collectively produce a set of data bits.

Abstract: A multiplier for computing a final product of a first operand and a second operand comprising a multiplier array for forming a product of the first operand and second operand in carry-save form; a carry-save adder for adding said carry-save partial products and an accumulatd sum to produce a carry and save values; a carry-lookahead adder for adding said carry and save values to produce a product value and a carry-out value; a general purpose adder for adding said carry-out and said product value to produce said final product.

Abstract: A method for computing an intermediate result in squaring a number using a multiplier circuit of predetermined operand size, the method comprising the steps of representing a number to be squared as a vector of binary digits; grouping the vector into successive segments each having a length of the predetermined operand size; multiplying a first segment value by a second segment value to generate a first product value; halving a second product value to generate a halved second product value; accumulating the first product value with the halved second product value to generate an accumulated value; and doubling the accumulated value to generate the intermediate result.

Abstract: The invention is an integrated circuit data storage array with storage cells disposed in an array of rows and columns with each cell having a number of subcells. The physical location of the subcells substantially reduces the space taken by horizontal data line used for accessing columns. This is accomplished by locating subcells of the same row number, the same bit number, and different column number adjacent to each other in the horizontal direction. As a result, a horizontal data line only extends between adjacent subcells and significantly reduces the wasted layout of multibit horizontal data lines.