Abstract: A method and apparatus are disclosed for selectively accessing and independently sizing connection identification tables within a network switch. Upon receipt of a data unit, such as an asynchronous transfer mode cell at an input port of an Input Output Module, a plurality of selection bits are inserted into the cell header which are used to select one of a plurality of connection identifiers. The VPI/VCI addresses are mapped into a connection identifier and the connection identifier is also inserted within the respective cell header. The connection identifier may comprise an unicast connection identifier, a multicast connection identifier, or a redundant unicast identifier. The unicast, multicast and redundant identifiers are either stored in separate tables at call setup and the tables are independently selectable via use of the selection bits stored within the cell header.

Abstract: First and second control processor cards are employed in conjunction with first and second switch fabric cards to interconnect Input/Output cards in a telecommunications switch. The control processor cards provide a portion of the functionality previously associated with switch fabric cards, such as exertion of control over allocation of bandwidth within the switch. The control processor cards also provide new functionality. In particular, each control processor card can configure both switch fabric cards. Redundant control processor cards and redundant switch fabric cards are employed to provide a switch that is less susceptible to failure than switches with only redundant switch fabric cards. Hence, failure of a control processor card and a switch fabric card can be sustained without resulting in switch failure. Timing control functions may also be provided by a separate timing module card.

Abstract: A packet scheduler is disclosed which provides a high degree of fairness in scheduling packets associated with different sessions. The scheduler also minimizes packet delay for packet transmission from a plurality of sessions which may have different requirements and may operate at different transfer rates. When a packet is received by the scheduler, the packet is assigned its own packet virtual start time based on whether the session has any pending packets and the values of the virtual finish time of the previous packet in the session and the packets arrival time. The scheduler then determines a virtual finish time of the packet by determining the transfer time required for the packet based upon its length and rate and by adding the transfer time to the packet virtual start time of the packet. The packet with the smallest virtual finish time is then scheduled for transfer.

Abstract: An apparatus and technique for facilitating mapping of a Multicast Circuit Identifier ("MID") to a Local Circuit Identifiers ("CID") is disclosed. Table entries for such mapping can be disposed in non-contiguous memory locations. A pointer is employed in ca h entry to indicate the location of any subsequent memory location associated with the MID. CIDs and associated memory locations are allocated only for ports that participate in a connection. To implement the apparatus and technique a first table provides an index into a second table based upon the MID. The second table includes entries having a port identification field, a pointer field and a CID field. The CID field indicates the CID associated with the port indicated by the port identification field. The CID is written to the header of the copy of the cell to be transmitted to the indicated port.

Abstract: A massively-parallel computer includes a plurality of processing nodes and at least one control node interconnected by a network. The network faciliates the transfer of data among the processing nodes and of commands from the control node to the processing nodes. Each each processing node includes an interface for transmitting data over, and receiving data and commands from, the network, at least one memory module for storing data, a node processor and an auxiliary processor. The node processor receives commands received by the interface and processes data in response thereto, in the process generating memory access requests for facilitating the retrieval of data from or storage of data in the memory module. The node processor further controlling the transfer of data over the network by the interface. The auxiliary processor is connected to the memory module and the node processor.

Abstract: A method of fairly and efficiently scheduling transmission of a packet from a plurality of sessions onto a network is presented. The method includes providing an input having a plurality of sessions, grouping the sessions into a plurality of classes, scheduling the classes with first level schedulers associated with one of the classes, scheduling the outputs of some of the first level schedulers with a second level scheduler, and prioritizing among the output of the remaining first level scheduler(s) and the output of the second level scheduler to provide an hierarchical scheduler output. The scheduler accepts traffic types at its input, and provides an output suitable for scheduling cell based traffic such as Asynchronous Transfer Mode (ATM) network traffic.

Abstract: A digital computer comprises a plurality of processing elements, a communications router, and a control network. Each processing element performs data processing operations in connection with commands, at least some of the processing elements performing the data processing operations in connection with the commands in messages they receive over the control network. Each processing element also generates and receives data transfer messages, each including an address portion containing an address, for transfer to another processing element as identified by the address. At least one of the processing elements further generates the control network messages for transfer over the communications router. The communications router comprises router nodes interconnected in the form of a "fat-tree," and the control network comprises control network nodes interconnected in the form of a tree, with the processing elements being connected at the leaf nodes of the respective communications router and control network.

Abstract: The present invention pertains to an apparatus for manipulating ATM cells. The apparatus comprises a memory array in which an entire ATM cell can be read or written in one read or write cycle. The apparatus is also comprised of a mechanism for reading or writing the entire ATM cell from or into the memory array. The present invention pertains to a method for switching an ATM cell. The method comprises the steps of receiving the ATM cell at a first input port of a switch from the ATM network. Then there can be the step of storing the ATM cell in one clock cycle in a memory array of the switch. Next there is the step of reading the ATM cell in the memory array in one clock cycle. Next there is the step of transferring the ATM cell from the memory array to a first output port of the switch. Next there is the step of transmitting the ATM cell from the first output port to the ATM network. The present invention pertains to a switch for an ATM cell.

Abstract: The present invention pertains to an apparatus for manipulating ATM cells. The apparatus comprises a memory array in which an entire ATM cell can be read or written in one read or write cycle. The apparatus is also comprised of a mechanism for reading or writing the entire ATM cell from or into the memory array. The present invention pertains to a method for switching an ATM cell. The method comprises the steps of receiving the ATM cell at a first input port of a switch from the ATM network. Then there can be the step of storing the ATM cell in one clock cycle in a memory array of the switch. Next there is the step of reading the ATM cell in the memory array in one clock cycle. Next there is the step of transferring the ATM cell from the memory array to a first output port of the switch. Next there is the step of transmitting the ATM cell from the first output port to the ATM network. The present invention pertains to a switch for an ATM cell.

Abstract: A digital computer having a plurality of message generating elements each generating and receiving messages and a network for transferring messages among the message generating elements. The network includes a plurality of node clusters interconnected in a tree pattern from a lower leaf level to an upper root level, each node cluster including at least one node group with node clusters in a level above at least one predetermined level having a larger number of node groups than node clusters of the predetermined level for transferring messages among the message generating elements.

Abstract: A digital computer includes a plurality of processing elements, a command processor, a diagnostic processor and a communications network. The processing elements each performs data processing and data communications operations in connection with commands. The processing elements also performing diagnostic operations in response to diagnostic operation requests and providing diagnostic results in response thereto. The command processor generates commands for the processing elements, and also performs diagnostic operations in response to diagnostic operation requests and providing diagnostic results in response thereto. The diagnostic processor generates diagnostic requests. The communication network includes three elements, including a data router, a control network and a diagnostic network. The data router is connected to the processing elements for facilitating the transfer of data among them during a data communications operation.

Abstract: A data coupling arrangement for successively receiving, in parallel, nibbles of respective data words, each nibble having a value, and for selectively coupling nibbles associated with one word in response to the relative values of the words. The selective coupling is determined by an identifier indication. The identifier indication is generated in response to a selected relationship between values represented by the nibbles from the respective words, until after nibbles are received whose values differ. At that point, the identifier indication is maintained in its condition thereby enabling the transfer of nibbles subsequently received from the same data word.