Patents by Inventor Mahmoud SAID

Mahmoud SAID has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130283101
    Abstract: The method of testing for presence of a bug a multithreaded computer program under verification combines the efficiency of testing with the reasoning power of satisfiability modulo theory (SMT) solvers for the verification of multithreaded programs under a user specified test vector. The method performs dynamic executions to obtain both under- and over-approximations of the program, represented as quantifier-free first order logic formulas. The formulas are then analyzed by an SMT solver which implicitly considers all possible thread interleavings. The symbolic analysis may return the following results: (1) it reports a real bug, (2) it proves that the program has no bug under the given input, or (3) it remains inconclusive because the analysis is based on abstractions. In the last case, a refinement procedure is presented that uses symbolic analysis to guide further executions.
    Type: Application
    Filed: April 17, 2013
    Publication date: October 24, 2013
    Applicants: The Regents of the University of Michigan, Western Michigan University Research Foundation
    Inventors: Zijiang Yang, Karem Sakallah, Mahmoud Said
  • Publication number: 20120179935
    Abstract: A computer implemented method for dynamic test generation for concurrent programs, which uses a combination of concrete and symbolic execution of the program to systematically cover all the intra-thread program branches and inter-thread interleavings of shared accesses. In addition, a coverage summary based pruning technique, which is a general framework for soundly removing both redundant paths and redundant interleavings and is capable of speeding up dynamic testing exponentially. This pruning framework also allows flexible trade-offs between pruning power and computational overhead to be exploited using various approximations.
    Type: Application
    Filed: January 11, 2012
    Publication date: July 12, 2012
    Applicant: NEC LABORATORIES AMERICA, INC.
    Inventors: Chao WANG, Mahmoud SAID, Aarti GUPTA, Vineet KAHLON, Nishant SINHA