Patents by Inventor Mahmud Assar
Mahmud Assar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20020112101Abstract: An interfacing system facilitating user-friendly connectivity in a selected operating mode between a host computer system and a flash memory card. The interfacing system includes an interface device and a flash memory card. The interfacing system features significantly expanded operating mode detection capability within the flash memory card and marked reduction in the incorrect detection of the operating mode. The interface device includes a first end for coupling to the host computer and a second end for coupling to the flash memory card, while supporting communication in the selected operating mode which is also supported by the host computer system. The flash memory card utilizes a fifty pin connection to interface with the host computer system through the interface device. The fifty pin connection of the flash memory card can be used with different interface devices in a variety of configurations such as a universal serial mode, PCMCIA mode, and ATA IDE mode.Type: ApplicationFiled: April 1, 2002Publication date: August 15, 2002Inventors: Petro Estakhri, Mahmud Assar
-
Patent number: 6411546Abstract: An embodiment of the present invention is disclosed to include a nonvolatile memory system for controlling erase operations performed on a nonvolatile memory array comprised of rows and columns, the nonvolatile memory array stores digital information organized into blocks with each block having one or more sectors of information and each sector having a user data field and an extension field and each sector stored within a row of the memory array. A controller circuit is coupled to a host circuit and is operative to perform erase operations on the nonvolatile memory array, the controller circuit erases an identified sector of information having a particular user data field and a particular extension field wherein the particular user field and the particular extension field are caused to be erased separately.Type: GrantFiled: May 5, 2000Date of Patent: June 25, 2002Assignee: Lexar Media, Inc.Inventors: Petro Estakhri, Siamack Nemazie, Mahmud Assar, Parviz Keshtbod
-
Patent number: 6404246Abstract: A system and method of generating an output signal of very precise frequency without the use of a crystal oscillator. An input signal is generated using any convenient such as an RC oscillator. A circuit for producing a frequency-controlled output signal comprises a phase lock loop having a VCO and a down counter. The down counter reduces the frequency of a VCO clock signal in accordance with a down count value. The down count value is loaded in a register and stored in non-volatile memory. The down count value is set during a calibration operation using a precision external clock signal. In this way, a clock signal with a highly precise frequency is generated without using a crystal oscillator.Type: GrantFiled: December 20, 2000Date of Patent: June 11, 2002Assignee: Lexa Media, Inc.Inventors: Petro Estakhri, Mahmud Assar, Parviz Keshtbod
-
Patent number: 6385667Abstract: An interfacing system facilitating user-friendly connectivity in a selected operating mode between a host computer system and a flash memory card. The interfacing system includes an interface device and a flash memory card. The interfacing system features significantly expanded operating mode detection capability within the flash memory card and marked reduction in the incorrect detection of the operating mode. The interface device includes a first end for coupling to the host computer and a second end for coupling to the flash memory card, while supporting communication in the selected operating mode which is also supported by the host computer system. The flash memory card utilizes a fifty pin connection to interface with the host computer system through the interface device. The fifty pin connection of the flash memory card can be used with different interface devices in a variety of configurations such as a universal serial mode, PCMCIA mode, and ATA IDE mode.Type: GrantFiled: January 20, 1999Date of Patent: May 7, 2002Assignee: Lexar Media, Inc.Inventors: Petro Estakhri, Mahmud Assar
-
Publication number: 20020040412Abstract: An interfacing system facilitating user-friendly connectivity in a selected operating mode between a host computer system and a flash memory card. The interfacing system includes an interface device and a flash memory card. The interfacing system features significantly expanded operating mode detection capability within the flash memory card and marked reduction in the incorrect detection of the operating mode. The interface device includes a first end for coupling to the host computer and a second end for coupling to the flash memory card, while supporting communication in the selected operating mode which is also supported by the host computer system. The flash memory card utilizes a fifty pin connection to interface with the host computer system through the interface device. The fifty pin connection of the flash memory card can be used with different interface devices in a variety of configurations such as a universal serial mode, PCMCIA mode, and ATA IDE mode.Type: ApplicationFiled: August 28, 2001Publication date: April 4, 2002Inventors: Petro Estakhri, Mahmud Assar
-
Patent number: 6182162Abstract: An improved compact flash memory card system includes an improved compact flash memory card desktop adapter and an improved compact flash memory card. The improved compact flash memory card desktop adapter utilizes a fifty pin socket to interface with the compact flash memory card. The desktop adapter also utilizes a plug adapter to interface with a computer. For more efficient communication between the improved compact flash memory card and the computer, the improved desktop adapter adopts the universal serial bus architecture. The improved compact flash memory card utilizes a fifty pin connection to interface with a computer through an interface device. The fifty pin connection of the flash memory card can be used with different interface devices in a variety of configurations such as a universal serial bus mode, PCMCIA mode, and ATA IDE mode. Each of these modes of operation require different protocols.Type: GrantFiled: March 2, 1998Date of Patent: January 30, 2001Assignee: Lexar Media, Inc.Inventors: Petro Estakhri, Mahmud Assar
-
Patent number: 5926055Abstract: An output circuit for producing 5 volt output signals from a chip that is manufactured in a 3 volt process, is provided with a control signal logic circuit, a pseudoground generating circuit, and an output signal generation circuit. The control signal logic circuit receives 3 volt data signals from the internal logic circuitry of the chip, and produces control signals as a function of these 3 volt data signals. The pseudoground generating circuit is coupled to the control signal logic circuit and generates a pseudoground greater than zero volts and intermediate output signals as a function of the control signals produced by the control signal logic circuit. The output signal generation circuit is coupled to the pseudoground generating circuit and generates the 5 volt output signals as a function of the intermediate output signals generated by the pseudoground generating circuit.Type: GrantFiled: December 20, 1996Date of Patent: July 20, 1999Assignee: Cirrus Logic, Inc.Inventors: Abdual Q. Kashmiri, Mahmud Assar
-
Patent number: 5924113Abstract: A nonvolatile semiconductor mass storage system and architecture can be substituted for a rotating hard disk. The system and architecture avoid an erase cycle each time information stored in the mass storage is changed. Erase cycles are avoided by programming an altered data file into an empty mass storage block rather than over itself as a hard disk would. Periodically the mass storage will need to be cleaned up. These advantages are achieved through the use of several flag, and a map to correlate a logical block address of a block to a physical address of that block. In particular, flags are provided for defective blocks, used blocks, and old versions of a block. An array of volatile memory is addressable according to the logical address and stores the physical address.Type: GrantFiled: May 29, 1998Date of Patent: July 13, 1999Assignee: Lexar Media, Inc.Inventors: Petro Estakhri, Mahmud Assar
-
Patent number: 5845313Abstract: A nonvolatile semiconductor mass storage system and architecture can be substituted for a rotating hard disk. The system and architecture avoid erase cycles each time information stored in the mass storage is changed. Erase cycle are avoided by programming an altered data file into an empty mass storage block rather than over itself as a hard disk would. Periodically, the mass storage will need to be cleaned up. These advantages are achieved through the use of several flags, and a map to correlate a logical block address of a block to a physical address of that block. In particular, flags are provided for defective blocks, used blocks, and old versions of a block.Type: GrantFiled: July 31, 1995Date of Patent: December 1, 1998Assignee: LexarInventors: Petro Estakhri, Mahmud Assar
-
Patent number: 5835935Abstract: A semiconductor non-volatile mass storage memory is partitioned into user files and system files. The system files partition is further subdivided into clusters, each cluster having a plurality of sectors. Each cluster stores the system file for a single predetermined LBA. As the information within the LBA is changed, the new information is written into an empty sector within the cluster. Once the cluster is filled, the system either erases for recycling the cluster or preferably locates an empty cluster and repeats the process with that new cluster. Once all the clusters are filled, all clusters containing old data are erased for recycling.Type: GrantFiled: September 13, 1995Date of Patent: November 10, 1998Assignee: Lexar Media, Inc.Inventors: Petro Estakhri, Mahmud Assar, Robert Alan Reid, Berhanu Iman
-
Patent number: 5818350Abstract: A circuit is provided for selecting one of plurality of integrated circuit chips with a minimum number of chip select signal lines. A first embodiment includes a plurality of paired address lines; each line in each pair provides a logical complementary signal. Only a selected one of the lines of each pair is coupled to integrated circuit. Each of the integrated circuits is coupled to a unique combination of these selected lines of the pairs. In a second embodiment a select signal is clocked by a controller from one of the integrated circuits to the next in a fashion similar to a shift register. Once the select signal is present in the desired integrated circuit, the controller then provides an enable signal to all the integrated circuits which enables only that desired integrated circuit. In yet another embodiment, the address lines are also used a chip select signal lines, one address line for each integrated circuit. A Chip.sub.-- select.sub.-- clock.sub.Type: GrantFiled: April 11, 1995Date of Patent: October 6, 1998Assignee: Lexar Microsystems Inc.Inventors: Petro Estakhri, Mahmud Assar
-
Patent number: 5818781Abstract: A computer card including a voltage detection circuit having Flash EEPROM devices and a controller device, the voltage detection circuit further including a variable voltage detector for determining the system voltage level provided by a power supply within the computer product and appropriately enabling a voltage regulator circuit for dividing the system voltage level to a level suited for operation by the Flash EEPROM devices and applying this operational voltage level to the Flash EEPROM devices. Upon determining the system voltage level provided by the power supply to be appropriately suited for operation of the Flash EEPROM devices, disabling the voltage regulator circuit and providing the system voltage level to the Flash EEPROM devices.Type: GrantFiled: November 13, 1996Date of Patent: October 6, 1998Assignee: LexarInventors: Petro Estakhri, Mahmud Assar, Boyd Gayle Pett
-
Patent number: 5596526Abstract: A multi-level NAND architecture non-volatile memory device reads and programs memory cells, each cell storing more than one bit of data, by comparing to a constant current level while selectively adjusting the gate voltage on the cell or cells being read or programmed. A plurality of read and write reference cells are provided each programmed to correspond to one each of the multi-level programming wherein during reading of the memory cells, the read reference cells provide the constant current level and during writing to the memory cells, the write reference cells provide the same. Furthermore, during a read operation, corresponding write reference cells are coupled to read reference cells to gauge the reading time associated with reading of memory cells.Type: GrantFiled: August 15, 1995Date of Patent: January 21, 1997Assignee: Lexar Microsystems, Inc.Inventors: Mahmud Assar, Parviz Keshtbod
-
Patent number: 5523724Abstract: A low power clocking circuit includes a crystal oscillator for generating a digital signal having a first frequency. The first frequency is relatively slow which allows the crystal oscillator to consume reduced power. The phase detector signal is coupled to control a charge pump circuit that generates a voltage on an output node for controlling a voltage controlled oscillator. The VCO generates a clock signal having a second frequency that is higher than the first frequency. The charge pump circuit includes an active mode and a power down mode and is operatively coupled between a first supply voltage and a second supply voltage. As typically provided, the charge pump includes a capacitor network coupled to the output node for maintaining the output voltage. The charge pump includes a voltage control circuit having an up input for increasing the output voltage and a down input for decreasing the output voltage.Type: GrantFiled: August 19, 1994Date of Patent: June 4, 1996Assignee: Cirrus Logic, Inc.Inventors: Mahmud Assar, Petro Estakhri, Boyd Pett
-
Flash memory mass storage architecture incorporating wear leveling technique without using cam cells
Patent number: 5485595Abstract: A semiconductor mass storage device can be substituted for a rotating hard disk. The device avoid an erase cycle each time information stored in the mass storage is changed. Erase cycles are avoided by programming an altered data file into an empty mass storage block rather than over itself as a hard disk would. Periodically, the mass storage will need to be cleaned up. Secondly, a circuit and method are provided for evenly using all blocks in the mass storage. These advantages are achieved through the use of several flags, a map to correlate a logical address of a block to a physical address of that block and a count register for each block. In particular, flags are provided for defective blocks, used blocks, old versions of a block, a count to determine the number of times a block has been erased and written and an erase inhibit flag. Reading is performed by providing the logical block address to the memory storage. The system sequentially compares the stored logical block addresses until it finds a match.Type: GrantFiled: October 4, 1993Date of Patent: January 16, 1996Assignee: Cirrus Logic, Inc.Inventors: Mahmud Assar, Petro Estakhri, Siamack Nemazie, Mahmood Mozaffari -
Patent number: 5479638Abstract: A semiconductor mass storage device can be substituted for a rotating hard disk. The device avoids an erase cycle each time information stored in the mass storage is changed. (The erase cycle is understood to include, fully programming the block to be erased, and then erasing the block.) Erase cycles are avoided by programming an altered data file into an empty mass storage block rather than over itself as a hard disk would. Periodically, the mass storage will need to be cleaned up. Secondly, a circuit for evenly using all blocks in the mass storage is provided. These advantages are achieved through the use of several flags, a map to directly correlate a logical address of a block to a physical address of that block and a count register for each block. In particular, flags are provided for defective blocks, used blocks, old version of a block, a count to determine the number of times a block has been erased and written and erase inhibit.Type: GrantFiled: March 26, 1993Date of Patent: December 26, 1995Assignee: Cirrus Logic, Inc.Inventors: Mahmud Assar, Siamack Nemazie, Petro Estakhri
-
Patent number: 5388083Abstract: A semiconductor mass storage system and architecture can be substituted for a rotating hard disk. The system and architecture avoid an erase cycle each time information stored in the mass storage is changed. (The erase cycle is understood to include, fully programming the block to be erased, and then erasing the block.) Erase cycles are avoided by programming an altered data file into an empty mass storage block rather than over itself as hard disk would. Periodically, the mass storage will need to be cleaned up. Secondly, all blocks in the mass storage are used evenly. These advantages are achieved through the use of several flags, a map to correlate a logical address of a block to a physical address of that block and a count register for each block. In particular, flags are provided for defective blocks, used blocks, old version of a block, a count to determine the number of times a block has been erased and written and erase inhibit flag.Type: GrantFiled: March 26, 1993Date of Patent: February 7, 1995Assignee: Cirrus Logic, Inc.Inventors: Mahmud Assar, Siamack Nemazie, Petro Estakhri
-
Patent number: 5300835Abstract: This invention describes the design and implementation of a low power CMOS bidirectional I/O buffer that translates low voltage core logic level signals into the highest logic level signals to drive the final output stage which outputs a selectable logic level signal. The invention further translates input signals of a variety of logic levels into low voltage core logic level signals. In either case, AC and DC power consumption is minimized in a mixed power supply environment that requires voltage translation to represent the proper binary logic levels.Type: GrantFiled: February 10, 1993Date of Patent: April 5, 1994Assignee: Cirrus Logic, Inc.Inventors: Mahmud Assar, Prakash C. Agarwal, Vlad Bril
-
Patent number: 5157618Abstract: Disclosed is a set of functional components (tiles), consisting in part of subgate elements, which, by their design, facilitate the creation of dense integrated circuits, without forfeiting the capability of modifying the functionality of individual tiles by late mask programming techniques. Overall densities approaching those obtained with hand-crafted, custom designs can be obtained in part because such components are designed to be tiled throughout a storage logic array, permitting the creation of orthogonal logic gates as well as individual gates (and more complex functions) the functionality of which is distributed horizontally, vertically and even in a zigzag fashion. Moreover, the transition time from prototype to high volume manufacturing is reduced significantly due to the ease with which even complex functions can be repaired and enhanced.Type: GrantFiled: February 28, 1990Date of Patent: October 20, 1992Assignee: Cirrus Logic, Inc.Inventors: H. Ravindra, Suhas S. Patil, Ernest S. Lin, Mahmud Assar, Dayakar Reddy