Patents by Inventor Mairtin O'Loingsigh

Mairtin O'Loingsigh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11630693
    Abstract: Technologies for power-aware scheduling include a computing device that receives network packets. The computing device classifies the network packets by priority level and then assigns each network packet to a performance group bin. The packets are assigned based on priority level and other performance criteria. The computing device schedules the network packets assigned to each performance group for processing by a processing engine such as a processor core. Network packets assigned to performance groups having a high priority level are scheduled for processing by processing engines with a high performance level. The computing device may select performance levels for processing engines based on processing workload of the network packets. The computing device may control the performance level of the processing engines, for example by controlling the frequency of processor cores. The processing workload may include packet encryption. Other embodiments are described and claimed.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: April 18, 2023
    Assignee: Intel Corporation
    Inventors: John Browne, Chris MacNamara, Tomasz Kantecki, Peter McCarthy, Liang Ma, Mairtin O'Loingsigh, Rory Sexton, John Griffin, Nemanja Marjanovic, David Hunt
  • Publication number: 20190042310
    Abstract: Technologies for power-aware scheduling include a computing device that receives network packets. The computing device classifies the network packets by priority level and then assigns each network packet to a performance group bin. The packets are assigned based on priority level and other performance criteria. The computing device schedules the network packets assigned to each performance group for processing by a processing engine such as a processor core. Network packets assigned to performance groups having a high priority level are scheduled for processing by processing engines with a high performance level. The computing device may select performance levels for processing engines based on processing workload of the network packets. The computing device may control the performance level of the processing engines, for example by controlling the frequency of processor cores. The processing workload may include packet encryption. Other embodiments are described and claimed.
    Type: Application
    Filed: April 12, 2018
    Publication date: February 7, 2019
    Inventors: John Browne, Chris MacNamara, Tomasz Kantecki, Peter McCarthy, Ma Liang, Mairtin O'Loingsigh, Rory Sexton, John Griffin, Nemanja Marjanovic, David Hunt