Patents by Inventor Majid Jalali Far
Majid Jalali Far has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10791203Abstract: A multi-protocol receiver for receiving at least one input signal comprises: a comparator, a protection controller, and a multi-stage current mode logic (“CML”) buffer. The comparator compares a reference voltage and a predefined voltage. At least one output of the comparator is coupled to at least one input of the protection controller. The multi-stage current mode logic buffer receives the input signal and the reference voltage. Outputs of the protection controller are coupled to control inputs of the multi-stage CML buffer for operating the multi-stage CML buffer to process the input signal and the reference signal.Type: GrantFiled: October 26, 2017Date of Patent: September 29, 2020Assignee: Synopsys, Inc.Inventors: Prasad Chalasani, Venkata N. S. N. Rao, Majid Jalali Far
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Patent number: 10742220Abstract: A programmable clock divider having reset circuits configured to receive a DP count comprises a first flip-flop having a clock input, a first output, and one of the DP inputs configured to receive a clock signal, a plurality of flip-flops connected to form a ripple counter configured to each receive a DP input, a clock input, and a reset input to provide a first output coupled to the clock input of a subsequent flip-flop of the plurality of flip-flops, each subsequent flip-flop having its clock input coupled to the first output of the preceding flip-flop, a first reset circuit coupled to the flip-flops configured to provide an out signal in response to the flip-flops obtaining the DP count, and a second reset circuit configured to provide a reset signal to the reset input of the plurality of flip-flops in response to the out signal from the first reset circuit.Type: GrantFiled: April 30, 2019Date of Patent: August 11, 2020Assignee: Synopsys, Inc.Inventors: Venkata N. S. N. Rao, Majid Jalali Far
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Patent number: 10498564Abstract: A high-speed serial link receiver system, comprises: an input terminal for receiving a signal; a pi-coil including a first inductor, a second inductor, and a third inductor; a first electrostatic discharge device (“ESD”); a second ESD; an on-die-termination (“ODT”); and a receiver. The first inductor, the second inductor, and the third inductor are serially connected. The input terminal is coupled to the first inductor. A serial connection between the first inductor and the second inductor is coupled to the first ESD device. A serial connection between the second inductor and the third inductor is coupled to the ODT. The second ESD device and the receiver are coupled to the third inductor.Type: GrantFiled: February 13, 2018Date of Patent: December 3, 2019Assignee: Invecas, Inc.Inventors: Majid Jalali Far, Venkata N. S. N. Rao
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Publication number: 20190253284Abstract: A high-speed serial link receiver system, comprises: an input terminal for receiving a signal; a pi-coil including a first inductor, a second inductor, and a third inductor; a first electrostatic discharge device (“ESD”); a second ESD; an on-die-termination (“ODT”); and a receiver. The first inductor, the second inductor, and the third inductor are serially connected. The input terminal is coupled to the first inductor. A serial connection between the first inductor and the second inductor is coupled to the first ESD device. A serial connection between the second inductor and the third inductor is coupled to the ODT. The second ESD device and the receiver are coupled to the third inductor.Type: ApplicationFiled: February 13, 2018Publication date: August 15, 2019Inventors: Majid Jalali Far, Venkata N.S.N. Rao
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Patent number: 10361684Abstract: A pulse-width-to-voltage (“PWV”) converter, comprises: a switch, a capacitor, a current source, and a current sink. The switch is operable by a signal. The current source, the current sink, and the switch are serially connected across a high voltage potential and a low voltage potential. An output node is coupled to a serial connection between the current source and the current sink. An end of the capacitor is coupled to the output node for converting a current into a control voltage indicative of a duty cycle of the signal.Type: GrantFiled: July 19, 2017Date of Patent: July 23, 2019Assignee: Invecas, Inc.Inventors: Venkata N. S. N. Rao, Majid Jalali Far, Prasad Chalasani, Aram Martirosyan
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Publication number: 20190132428Abstract: A multi-protocol receiver for receiving at least one input signal comprises: a comparator, a protection controller, and a multi-stage current mode logic (“CML”) buffer. The comparator compares a reference voltage and a predefined voltage. At least one output of the comparator is coupled to at least one input of the protection controller. The multi-stage current mode logic buffer receives the input signal and the reference voltage. Outputs of the protection controller are coupled to control inputs of the multi-stage CML buffer for operating the multi-stage CML buffer to process the input signal and the reference signal.Type: ApplicationFiled: October 26, 2017Publication date: May 2, 2019Inventors: Prasad Chalasani, Venkata N.S.N. Rao, Majid Jalali Far
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Publication number: 20190028090Abstract: A pulse-width-to-voltage (“PWV”) converter, comprises: a switch, a capacitor, a current source, and a current sink. The switch is operable by a signal. The current source, the current sink, and the switch are serially connected across a high voltage potential and a low voltage potential. An output node is coupled to a serial connection between the current source and the current sink. An end of the capacitor is coupled to the output node for converting a current into a control voltage indicative of a duty cycle of the signal.Type: ApplicationFiled: July 19, 2017Publication date: January 24, 2019Inventors: Venkata N.S.N. Rao, Majid Jalali Far, Prasad Chalasani, Aram Martirosyan
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Patent number: 10094859Abstract: A power voltage detector comprises voltage sensors for sensing supply voltages; and a logic. The logic combines the sensed supply voltages to generate a logic output indicative of whether the sensed supply voltages have met one or more predefined thresholds. Each of the voltage sensors has diode-connected transistors and passive resistance. The diode-connected transistors and the passive resistance are serially connected for generating an output, where the output is coupled to an input of the logic.Type: GrantFiled: July 19, 2017Date of Patent: October 9, 2018Assignee: Invecas, Inc.Inventors: Venkata N. S. N. Rao, Prasad Chalasani, Majid Jalali Far
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Patent number: 10061340Abstract: A bandgap reference voltage generator, comprises: a bias circuit configured to generate a start signal; a startup circuit having at least two serially-connected transistors configured to receive the start signal; a proportional-to-absolute-temperature (“PTAT”) generation circuit having a first current mirror, an amplifier, a resistor, and transistors; and a complementary-to-absolute-temperature (“CTAT”) generation circuit having a second current mirror, a passive network of resistors, and at least one transistor. The at least two serially-connected transistors are connected across a first input of the amplifier and a second input of the amplifier. An output of the amplifier is coupled to the first current mirror and the second current mirror. The passive network of resistors is coupled across outputs of the second current mirror. The CTAT generation circuit has an output node for outputting a bandgap reference voltage.Type: GrantFiled: January 24, 2018Date of Patent: August 28, 2018Assignee: Invecas, Inc.Inventors: Venkata N. S. N. Rao, Majid Jalali Far