Patents by Inventor Makaram Raghunandan
Makaram Raghunandan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140003602Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.Type: ApplicationFiled: August 29, 2013Publication date: January 2, 2014Inventors: SHAY GUERON, WAJDI K. FEGHALI, VINODH GOPAL, MAKARAM RAGHUNANDAN, MARTIN G. DIXON, SRINIVAS CHENNUPATY, MICHAELE E. KOUNAVIS
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Patent number: 8538015Abstract: A flexible instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.Type: GrantFiled: March 28, 2007Date of Patent: September 17, 2013Assignee: Intel CorporationInventors: Shay Gueron, Wajdi K. Feghali, Vinodh Gopal, Makaram Raghunandan, Martin G. Dixon, Srinivas Chennupaty, Michael E. Kounavis
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Patent number: 8189792Abstract: In one embodiment, the present invention includes a processor having logic to perform a round of a cryptographic algorithm responsive to first and second round micro-operations to perform the round on first and second pairs of columns, where the logic includes dual datapaths that are half the width of the cryptographic algorithm width (or smaller). Additional logic may be used to combine the results of the first and second round micro-operations to obtain a round result. Other embodiments are described and claimed.Type: GrantFiled: December 28, 2007Date of Patent: May 29, 2012Assignee: Intel CorporationInventors: Brent Boswell, Kirk Yap, Gilbert Wolrich, Wajdi Feghali, Vinodh Gopal, Srinivas Chennupaty, Makaram Raghunandan
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Patent number: 7953221Abstract: In one embodiment, the present disclosure provides a method capable of processing a variety of different operations. A method according to one embodiment may include loading configuration data from a shared memory unit into a hardware configuration register, the hardware configuration register located within circuitry included within a hardware accelerator unit. The method may also include issuing a command set from a microengine to the hardware accelerator unit having the circuitry. The method may additionally include receiving the command set at the circuitry from the microengine, the command set configured to allow for the processing of a variety of different operations. The method may further include processing an appropriate operation based upon the configuration data loaded into the hardware configuration register. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.Type: GrantFiled: December 28, 2006Date of Patent: May 31, 2011Assignee: Intel CorporationInventors: Wajdi Feghali, Stephanie Hirnak, Makaram Raghunandan, Yogesh Bansal, Kirk Yap, Gilbert M. Wolrich
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Patent number: 7720854Abstract: Techniques are described herein that can be used to access entries in a packed table. An unpacked table includes empty and filled elements. Filled elements can be accumulated and included in a packed table. An element in the packed table can be accessed by considering the location the element would have been located in the unpacked table. The location can be used to determine the location of the element in the packed table.Type: GrantFiled: August 25, 2006Date of Patent: May 18, 2010Assignee: Intel CorporationInventor: Makaram Raghunandan
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Publication number: 20090168999Abstract: In one embodiment, the present invention includes a processor having logic to perform a round of a cryptographic algorithm responsive to first and second round micro-operations to perform the round on first and second pairs of columns, where the logic includes dual datapaths that are half the width of the cryptographic algorithm width (or smaller). Additional logic may be used to combine the results of the first and second round micro-operations to obtain a round result. Other embodiments are described and claimed.Type: ApplicationFiled: December 28, 2007Publication date: July 2, 2009Inventors: Brent Boswell, Kirk Yap, Gilbert Wolrich, Wajdi Feghali, Vinodh Gopal, Srinivas Chennupaty, Makaram Raghunandan
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Publication number: 20080240426Abstract: A flexible aes instruction set for a general purpose processor is provided. The instruction set includes instructions to perform a “one round” pass for aes encryption or decryption and also includes instructions to perform key generation. An immediate may be used to indicate round number and key size for key generation for 128/192/256 bit keys. The flexible aes instruction set enables full use of pipelining capabilities because it does not require tracking of implicit registers.Type: ApplicationFiled: March 28, 2007Publication date: October 2, 2008Inventors: Shay Gueron, Wajdi K. Feghali, Vinodh Gopal, Makaram Raghunandan, Martin G. Dixon, Srinivas Chennupaty, Michael E. Kounavis
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Publication number: 20080159528Abstract: In one embodiment, the present disclosure provides a method capable of processing a variety of different operations. A method according to one embodiment may include loading configuration data from a shared memory unit into a hardware configuration register, the hardware configuration register located within circuitry included within a hardware accelerator unit. The method may also include issuing a command set from a microengine to the hardware accelerator unit having the circuitry. The method may additionally include receiving the command set at the circuitry from the microengine, the command set configured to allow for the processing of a variety of different operations. The method may further include processing an appropriate operation based upon the configuration data loaded into the hardware configuration register. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.Type: ApplicationFiled: December 28, 2006Publication date: July 3, 2008Applicant: INTEL CORPORATIONInventors: Wajdi Feghali, Stephanie Hirnak, Makaram Raghunandan, Yogesh Bansal, Kirk Yap, Gilbert M. Wolrich
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Patent number: 7380168Abstract: According to some embodiments, execution information is received from a first development tool. Execution information is also received from a second development tool. Based on the first execution information and the second execution information, operation of the first development tool may be controlled. According to some embodiments, the first and second development tools are associated with different processor architectures.Type: GrantFiled: June 30, 2005Date of Patent: May 27, 2008Assignee: Intel CorporationInventors: Makaram Raghunandan, Rajendra S. Yavatkar, Shou C. Chen, Dave Edwards, Geoffrey R. Gustafson
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Publication number: 20080052304Abstract: Techniques are described herein that can be used to access entries in a packed table. An unpacked table includes empty and filled elements. Filled elements can be accumulated and included in a packed table. An element in the packed table can be accessed by considering the location the element would have been located in the unpacked table.Type: ApplicationFiled: August 25, 2006Publication date: February 28, 2008Inventor: Makaram Raghunandan
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Publication number: 20070156928Abstract: A token passing mechanism reduces unnecessary thread stalls in a multithreaded microprocessor system. In a multithreaded microprocessor system, in order processing for critical sections is managed through the use of tokens with access to each critical section restricted to the thread having the token associated with the critical section. A token handler maintains a token skip indicator per token that allows a thread that does not need a critical section to forward the token associated with that critical section to a next thread prior to reaching the critical section.Type: ApplicationFiled: December 30, 2005Publication date: July 5, 2007Inventor: Makaram Raghunandan
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Publication number: 20070006171Abstract: According to some embodiments, execution information is received from a first development tool. Execution information is also received from a second development tool. Based on the first execution information and the second execution information, operation of the first development tool may be controlled. According to some embodiments, the first and second development tools are associated with different processor architectures.Type: ApplicationFiled: June 30, 2005Publication date: January 4, 2007Inventors: Makaram Raghunandan, Rajendra Yavatkar, Shou Chen, Dave Edwards, Geoffrey Gustafson
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Publication number: 20060112397Abstract: In general, in one aspect, the disclosure describes a method that includes providing a user interface common to multiple development tools, different ones of the development tools dedicated to different processor architectures. The method also includes enabling communications between the user interface and the development tools.Type: ApplicationFiled: November 18, 2004Publication date: May 25, 2006Inventors: Makaram Raghunandan, Rajendra Yavatkar, Mark Skarpness
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Publication number: 20040264479Abstract: A method of generating a trie having a reduced number of trie blocks. An algorithm identifies data to be to be added to a trie. The algorithm separates the data into portions having sizes based, at least in part, on sizes related to trie blocks in the trie. The algorithm indicates in a trie entry of a first trie block, wherein a first portion of the prefix identifies the trie entry, that a second portion of the prefix is stored in a pruned-trie entry. The algorithm indicates in the trie entry of the first trie block a location of the pruned-trie entry, and stores the second portion of the prefix in the pruned-trie entry. The algorithm indicates in the pruned-trie entry the position the second portion occupies relative to other portions of the data.Type: ApplicationFiled: June 30, 2003Publication date: December 30, 2004Inventor: Makaram Raghunandan
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Publication number: 20040128401Abstract: Scheduling the processing of threads by scheduling a datagram from an input queue among a plurality of input queues to a thread for processing. The scheduling includes computing an output position in an output queue, communicating with a plurality of threads for processing, and assigning the datagram to one of said plurality of threads for processing. After processing the datagram, the processing thread enqueus the datagram in the output queues at the output position specified by the scheduled output position.Type: ApplicationFiled: December 31, 2002Publication date: July 1, 2004Inventors: Michael Fallon, Makaram Raghunandan
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Publication number: 20030165116Abstract: Shaping data transmitted in a communication system includes determining whether to authorize transmission of received data having a variable size within a predetermined range. The determination is based on whether a predetermined amount of a time-based variable has substantially elapsed, the predetermined amount being related to a rate shaping criterion, and the determination is made without regard to the size of the received data.Type: ApplicationFiled: March 1, 2002Publication date: September 4, 2003Inventors: Michael F. Fallon, Makaram Raghunandan