Patents by Inventor MAKARAND RAMKRISHNA KULKARNI
MAKARAND RAMKRISHNA KULKARNI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955479Abstract: A packaged semiconductor device includes a molded interconnect substrate having a signal layer including a first channel and a second channel on a dielectric layer with vias, and a bottom metal layer for providing a ground return path. The signal layer includes contact pads, traces of the first and second channel include narrowed trace regions, and the bottom metal layer includes a patterned layer including ground cut regions. DC blocking capacitors are in series within the traces of the first and second channel for providing AC coupling that have one plate over one of the ground cuts. An integrated circuit (IC) includes a first and a second differential input channel coupled to receive an output from the DC blocking capacitors, with a bump array thereon flip chip mounted to the contact pads to provide first and second differential output signals.Type: GrantFiled: October 29, 2019Date of Patent: April 9, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Yiqi Tang, Rajen Manicon Murugan, Makarand Ramkrishna Kulkarni
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Publication number: 20240071889Abstract: A lead for a surface mount package for a semiconductor device, and the surface mount package employing the same. In one example, the lead includes a central segment with a first side and a second side, a first extension from a portion of the first side, and a second extension from a portion of the second side. The lead also includes a recess extending through a portion of the central segment, the first extension and the second extension.Type: ApplicationFiled: August 29, 2022Publication date: February 29, 2024Applicant: Texas Instruments IncorporatedInventors: Naweed Anjum, Michael Gerald Amaro, Makarand Ramkrishna Kulkarni
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Publication number: 20240047330Abstract: In some examples, a semiconductor package comprises a multi-layer package substrate. The multi-layer package substrate includes first and second metal layers, the first metal layer positioned above the second metal layer and coupled to the second metal layer by way of a via. The substrate also includes a dielectric covering at least part of the first and second metal layers and the via. The package includes a plated metal layer plated on at least part of the first metal layer and positioned above the dielectric, a combination of the first metal layer and the plated metal layer being thicker than the second metal layer. The package includes a semiconductor die having a device side, the device side vertically aligned with and coupled to the plated metal layer.Type: ApplicationFiled: October 10, 2023Publication date: February 8, 2024Inventors: Jonathan Almeria NOQUIL, Makarand Ramkrishna KULKARNI, Osvaldo Jorge LOPEZ, Yiqi TANG, Rajen Manicon MURUGAN, Liang WAN
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Patent number: 11784114Abstract: In some examples, a semiconductor package comprises a multi-layer package substrate. The multi-layer package substrate includes first and second metal layers, the first metal layer positioned above the second metal layer and coupled to the second metal layer by way of a via. The substrate also includes a dielectric covering at least part of the first and second metal layers and the via. The package includes a plated metal layer plated on at least part of the first metal layer and positioned above the dielectric, a combination of the first metal layer and the plated metal layer being thicker than the second metal layer. The package includes a semiconductor die having a device side, the device side vertically aligned with and coupled to the plated metal layer.Type: GrantFiled: May 28, 2021Date of Patent: October 10, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jonathan Almeria Noquil, Makarand Ramkrishna Kulkarni, Osvaldo Jorge Lopez, Yiqi Tang, Rajen Manicon Murugan, Liang Wan
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Publication number: 20230063343Abstract: An electronic device includes a multilevel package substrate with first and second levels extending in planes of first and second directions and spaced apart from one another along a third direction, the first level having a first side with landing areas and the second level having a second side with conductive landing pads. The electronic device includes a die with conductive terminals electrically coupled to respective ones of the landing areas, as well as solder balls attached to respective ones of the landing pads, and a package structure that encloses the die and a portion of the multilevel package substrate.Type: ApplicationFiled: August 24, 2021Publication date: March 2, 2023Applicant: Texas Instruments IncorporatedInventors: Rajen Manicon Murugan, Yiqi Tang, Jonathan Almeria Noquil, Makarand Ramkrishna Kulkarni
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Publication number: 20220384353Abstract: A semiconductor package includes a first layer including a semiconductor die and a shunt embedded within a first dielectric substrate layer, and metal pillars extending therethrough. The semiconductor package further includes a second layer stacked on the first layer, the second layer including a metal trace patterned on the first dielectric substrate layer, and a second dielectric substrate layer over the metal trace. The metal trace electrically connects a first portion of the shunt to a first metal pillar of the metal pillars and electrically connects a second portion of the shunt to a second metal pillar of the metal pillars. The semiconductor package further includes a base layer opposite the second layer relative the first layer, the base layer forming exposed electrical contact pads for the semiconductor package, the electrical contact pads providing electrical connections to the shunt, the metal pillars, and the semiconductor die.Type: ApplicationFiled: October 13, 2021Publication date: December 1, 2022Inventors: Yiqi Tang, Rajen Manicon Murugan, Liang Wan, Makarand Ramkrishna Kulkarni, Jie Chen, Steven Alfred Kummerl
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Patent number: 11430720Abstract: A lead for a surface mount package for a semiconductor device, and the surface mount package employing the same. In one example, the lead includes a central segment with a first side and a second side, a first extension from a portion of the first side, and a second extension from a portion of the second side. The lead also includes a recess extending through a portion of the central segment, the first extension and the second extension.Type: GrantFiled: July 27, 2020Date of Patent: August 30, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Naweed Anjum, Michael Gerald Amaro, Makarand Ramkrishna Kulkarni
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Publication number: 20220209391Abstract: An antenna in package (AIP) 400 includes an IC die 120 including bond pads 121 and a package substrate including the IC die mounted up and being completely embedded therein. The package substrate includes a top layer 418 including a top dielectric layer 418b, a top metal layer 418a including an antenna 418a1, and a bottom layer 415 including a bottom dielectric 415b and a bottom metal layer 415a including contact pads including a first contact pad 415a1, and filled vias 415c, 417c. The bond pads are electrically coupled by a connection including a filled via(s) for connecting to the top metal layer and/or the bottom metal layer. Metal pillars including a first metal pillar 132a are electrically are coupled to the first contact pad, and at least one filled via is electrically coupled to the first metal pillar for providing a transmission line from the first contact pad to the antenna.Type: ApplicationFiled: December 30, 2020Publication date: June 30, 2022Inventors: Yiqi Tang, Makarand Ramkrishna Kulkarni, Liang Wan, Rajen Manicon Murugan
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Publication number: 20220181241Abstract: In some examples, a semiconductor package comprises a multi-layer package substrate. The multi-layer package substrate includes first and second metal layers, the first metal layer positioned above the second metal layer and coupled to the second metal layer by way of a via. The substrate also includes a dielectric covering at least part of the first and second metal layers and the via. The package includes a plated metal layer plated on at least part of the first metal layer and positioned above the dielectric, a combination of the first metal layer and the plated metal layer being thicker than the second metal layer. The package includes a semiconductor die having a device side, the device side vertically aligned with and coupled to the plated metal layer.Type: ApplicationFiled: May 28, 2021Publication date: June 9, 2022Inventors: Jonathan Almeria NOQUIL, Makarand Ramkrishna KULKARNI, Osvaldo Jorge LOPEZ, Yiqi TANG, Rajen Manicon MURUGAN, Liang WAN
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Publication number: 20220028767Abstract: A lead for a surface mount package for a semiconductor device, and the surface mount package employing the same. In one example, the lead includes a central segment with a first side and a second side, a first extension from a portion of the first side, and a second extension from a portion of the second side. The lead also includes a recess extending through a portion of the central segment, the first extension and the second extension.Type: ApplicationFiled: July 27, 2020Publication date: January 27, 2022Applicant: Texas Instruments IncorporatedInventors: Naweed Anjum, Michael Gerald Amaro, Makarand Ramkrishna Kulkarni
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Patent number: 11217460Abstract: A method of assembling a flip chip IC package includes applying core underfill material to a surface of a package substrate in a pattern including an area corresponding to a core region of an IC die thereon that is to be attached, that excludes of an area corresponding to corners of the IC die. The IC die is bonded to the package substrate by pushing the IC die with a sufficient force for the core underfill material is displaced laterally by the bumps so that the bumps contact the land pads. After the pushing the corners of the IC die are not on the core underfill. Edge underfilling includes dispensing a second underfill material that is curable liquid to fill an area under the corners of the IC die. The second underfill material is cured resulting in it having a higher fracture strength as compared to the core underfill.Type: GrantFiled: May 9, 2018Date of Patent: January 4, 2022Assignee: Texas Instruments IncorporatedInventors: Makarand Ramkrishna Kulkarni, Tae Kim
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Patent number: 11160163Abstract: An electronic substrate includes a dielectric core, a first conducting layer on a first side of the core and a second conducting layer on the second side of the core opposite the first side. At least one differential coaxial through-via includes a first inner signal through-via that is at least electrical conductor lined for a first signal path and at least a second inner signal through-via that is also at least electrical conductor lined positioned side-by-side and being dielectrically isolated from the first inner signal through-via for a second signal path. An annular-shaped outer ground shield enclosure is at least conductor lined that surrounds and is dielectrically isolated from both the first and second inner signal through-vias.Type: GrantFiled: November 17, 2017Date of Patent: October 26, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Snehamay Sinha, Tapobrata Bandyopadhyay, Makarand Ramkrishna Kulkarni
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Publication number: 20210320093Abstract: A multichip module (MCM) power package includes a multilayer routable leadframe substrate (MRLF) substrate including a first and a second RLF layer. A multilayer extending via extends from the first into the second RLF layer. A first vertical FET has a side flipchip attached to a bottom side of the second RLF. A second vertical FET has a side flipchip attached to a bottom side of the second RLF layer, and contacts the multilayer extending via. A controller integrated circuit (IC) is flipchip attached a top side of the MRLF substrate at least partially over the first vertical FET. A top mold compound is on a top side of the MRLF substrate lateral to the controller IC that is lateral to a metal pad on the multilayer extending via. A bottom side of the first and second vertical FET are exposed by a bottom mold compound layer.Type: ApplicationFiled: June 24, 2021Publication date: October 14, 2021Inventors: Jonathan Almeria Noquil, Makarand Ramkrishna Kulkarni
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Patent number: 11081472Abstract: A multichip module (MCM) power package includes a multilayer routable leadframe substrate (MRLF) substrate including a first and a second RLF layer. A multilayer extending via extends from the first into the second RLF layer. A first vertical FET has a side flipchip attached to a bottom side of the second RLF. A second vertical FET has a side flipchip attached to a bottom side of the second RLF layer, and contacts the multilayer extending via. A controller integrated circuit (IC) is flipchip attached a top side of the MRLF substrate at least partially over the first vertical FET. A top mold compound is on a top side of the MRLF substrate lateral to the controller IC that is lateral to a metal pad on the multilayer extending via. A bottom side of the first and second vertical FET are exposed by a bottom mold compound layer.Type: GrantFiled: September 18, 2019Date of Patent: August 3, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jonathan Almeria Noquil, Makarand Ramkrishna Kulkarni
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Publication number: 20210082889Abstract: A multichip module (MCM) power package includes a multilayer routable leadframe substrate (MRLF) substrate including a first and a second RLF layer. A multilayer extending via extends from the first into the second RLF layer. A first vertical FET has a side flipchip attached to a bottom side of the second RLF. A second vertical FET has a side flipchip attached to a bottom side of the second RLF layer, and contacts the multilayer extending via. A controller integrated circuit (IC) is flipchip attached a top side of the MRLF substrate at least partially over the first vertical FET. A top mold compound is on a top side of the MRLF substrate lateral to the controller IC that is lateral to a metal pad on the multilayer extending via. A bottom side of the first and second vertical FET are exposed by a bottom mold compound layer.Type: ApplicationFiled: September 18, 2019Publication date: March 18, 2021Inventors: Jonathan Almeria Noquil, Makarand Ramkrishna Kulkarni
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Publication number: 20200381342Abstract: In examples, a semiconductor package comprises a first conductive terminal; a second conductive terminal; a conductive pathway coupling the first and second conductive terminals, the conductive pathway configured to generate a magnetic field; a semiconductor die including a circuit configured to detect the magnetic field; and first and second polyimide layers positioned between the conductive pathway and the semiconductor die.Type: ApplicationFiled: May 28, 2020Publication date: December 3, 2020Inventors: YongSeok PARK, Makarand Ramkrishna KULKARNI, Ricky Alan JACKSON, Byron Lovell WILLIAMS, Thomas Dyer BONIFIELD
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Publication number: 20200066716Abstract: A packaged semiconductor device includes a molded interconnect substrate having a signal layer including a first channel and a second channel on a dielectric layer with vias, and a bottom metal layer for providing a ground return path. The signal layer includes contact pads, traces of the first and second channel include narrowed trace regions, and the bottom metal layer includes a patterned layer including ground cut regions. DC blocking capacitors are in series within the traces of the first and second channel for providing AC coupling that have one plate over one of the ground cuts. An integrated circuit (IC) includes a first and a second differential input channel coupled to receive an output from the DC blocking capacitors, with a bump array thereon flip chip mounted to the contact pads to provide first and second differential output signals.Type: ApplicationFiled: October 29, 2019Publication date: February 27, 2020Inventors: Yiqi Tang, Rajen Manicon Murugan, Makarand Ramkrishna Kulkarni
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Publication number: 20190363080Abstract: A packaged semiconductor device includes a molded interconnect substrate having a signal layer including a first channel and a second channel on a dielectric layer with vias, and a bottom metal layer for providing a ground return path. The signal layer includes contact pads, traces of the first and second channel include narrowed trace regions, and the bottom metal layer includes a patterned layer including ground cut regions. DC blocking capacitors are in series within the traces of the first and second channel for providing AC coupling that have one plate over one of the ground cuts. An integrated circuit (IC) includes a first and a second differential input channel coupled to receive an output from the DC blocking capacitors, with a bump array thereon flip chip mounted to the contact pads to provide first and second differential output signals.Type: ApplicationFiled: July 17, 2018Publication date: November 28, 2019Inventors: YIQI TANG, RAJEN MANICON MURUGAN, MAKARAND RAMKRISHNA KULKARNI
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Publication number: 20190348303Abstract: A method of assembling a flip chip IC package includes applying core underfill material to a surface of a package substrate in a pattern including an area corresponding to a core region of an IC die thereon that is to be attached, that excludes of an area corresponding to corners of the IC die. The IC die is bonded to the package substrate by pushing the IC die with a sufficient force for the core underfill material is displaced laterally by the bumps so that the bumps contact the land pads. After the pushing the corners of the IC die are not on the core underfill. Edge underfilling includes dispensing a second underfill material that is curable liquid to fill an area under the corners of the IC die. The second underfill material is cured resulting in it having a higher fracture strength as compared to the core underfill.Type: ApplicationFiled: May 9, 2018Publication date: November 14, 2019Inventors: MAKARAND RAMKRISHNA KULKARNI, TAE KIM
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Patent number: 10475786Abstract: A packaged semiconductor device includes a molded interconnect substrate having a signal layer including a first channel and a second channel on a dielectric layer with vias, and a bottom metal layer for providing a ground return path. The signal layer includes contact pads, traces of the first and second channel include narrowed trace regions, and the bottom metal layer includes a patterned layer including ground cut regions. DC blocking capacitors are in series within the traces of the first and second channel for providing AC coupling that have one plate over one of the ground cuts. An integrated circuit (IC) includes a first and a second differential input channel coupled to receive an output from the DC blocking capacitors, with a bump array thereon flip chip mounted to the contact pads to provide first and second differential output signals.Type: GrantFiled: July 17, 2018Date of Patent: November 12, 2019Assignee: Texas Instruments IncorporatedInventors: Yiqi Tang, Rajen Manicon Murugan, Makarand Ramkrishna Kulkarni