Abstract: A semiconductor memory having dynamic memory cells includes a determining circuit for determining whether or not it is necessary to refresh the dynamic memory cells, and only when it is necessary, outputting a refresh execution signal in response to a refresh request signal from an external circuit, and a circuit for executing a refresh operation in response to the refresh execution signal. Even if the refresh request signal is supplied, a refresh operation is not executed unless the determining circuit determines that the refresh operation is necessary, thus dispensing with unnecessary refresh operations. Preferably, the determining circuit includes a timer which outputs a signal at every predetermined period. Only when the signal is output from the timer, is the refresh request signal from an external circuit accepted and the refresh execution signal output.

Abstract: An output circuit for outputting an output signal in response to an input signal having first and second voltage levels, comprises first circuit responsive to the input signal for generating a first signal including a low impedance portion corresponding to the duration of the second level of the input signal. A second circuit responsive to the input signal is further provided to supply a second signal including a low impedance portion which exists after the duration of the second voltage level of the input signal. The first and the second signals are combined to produce the output signal.

Abstract: A semiconductor integrated circuit which is capable of being selectively set to an operation mode or a stand-by mode has an oscillating circuit for outputting a frequency signal for controlling the operation of said semiconductor circuit. The output side of the oscillating circuit is connected to a timing generator through a first NAND gate. To the other input terminal of the first NAND gate is supplied information of an oscillation stop request (stand-by mode) due to reduction of the voltage of a power supply connected to the outside of the semiconductor integrated circuit and an oscillation start request (operation mode) accompanying the recovery of the voltage supply circuit or the oscillation from the timing generator through a second NAND gate. Thus, when the supply voltage is reduced, a logic low level signal is supplied from the second NAND gate to the first NAND gate to block the output of the oscillating circuit.A counter is connected to the oscillating circuit.