Patents by Inventor Makio Higashi
Makio Higashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7840299Abstract: When a trouble occurs in a substrate treatment apparatus, the substrate existing in the substrate treatment apparatus is quickly collected without exerting adverse effects on the subsequent substrate treatment to resume the substrate treatment early. At the time of occurrence of trouble in a coating and developing treatment apparatus, all of the substrates in the coating and developing treatment apparatus are collected to a transfer-in/out section using a transfer unit in the apparatus. In this event, each transfer unit transfers the substrate from each position at the time of occurrence of trouble in a direction toward the transfer-in/out section for collection. Further, the substrate under treatment in the treatment unit at the time of occurrence of trouble is collected after the treatment is finished.Type: GrantFiled: June 23, 2005Date of Patent: November 23, 2010Assignee: Tokyo Electron LimitedInventors: Makio Higashi, Akira Miyata, Yoshitaka Hara
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Publication number: 20090149982Abstract: In the present invention, when a ghost wafer which is not recognized by a control unit on a coating and developing treatment apparatus side is carried out of another apparatus which is connected to the coating and developing treatment apparatus, the ghost wafer is temporarily housed in a buffer cassette on the coating and developing treatment apparatus side. The ghost wafer in the buffer cassette is then collected into a carry-in/out section on the coating and developing treatment apparatus side through use of a carrier unit at a timing which does not affect processing of other wafers in a break between lots. According to the present invention, the ghost wafer occurred in the coating and developing treatment apparatus can be collected without suspension of processing of other ordinary substrates.Type: ApplicationFiled: January 8, 2009Publication date: June 11, 2009Inventors: Makio Higashi, Akira Miyata, Shinichi Seki
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Patent number: 7383093Abstract: A substrate processing apparatus of the invention comprises a transfer schedule creating section, a transfer schedule storage section, a transfer control section which controls, by referring to the transfer schedule, plural transfer mechanisms so as to transfer a substrate written into data of a cycle containing plural transfer operations to a module corresponding to the substrate, and a standby position control section which operates such that, by referring to the transfer schedule stored in the transfer schedule storage section, after one transfer mechanism completes the transfer operations allotted to itself in one cycle, and during a period that another transfer mechanism executes the transfer operations allotted to itself in the one cycle, the standby position control section moves the one transfer mechanism and puts the one transfer mechanism on standby at a front module when viewed in the transfer operation in the modules allotted thereto in a next cycle.Type: GrantFiled: September 25, 2006Date of Patent: June 3, 2008Assignee: Tokyo Electron LimitedInventors: Makio Higashi, Akira Miyata
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Patent number: 7379785Abstract: In a coating and developing apparatus that forms a resist film on substrates such as semiconductor wafers, and develops substrates exposed by an aligner, times after the aligner unloads substrates until heating units (PEB) start heating the substrates are kept uniform. Exposed wafers are prevented from being left stagnant in an interface portion disposed between a region in which resist is coated and developed and the aligner. In the region in which resist is coated and developed, a first transferring means that successively executes transportation cycles to transfer substrates from upstream side modules to downstream side modules in a flow of processes of substrates. N heating units (PEB) are disposed (n is for example 5). Exposed wafers loaded into the heating units (PEB) are unloaded by the first transferring means after (n?1) cycles including the transferring cycle of the first transferring means have elapsed.Type: GrantFiled: November 18, 2003Date of Patent: May 27, 2008Assignee: Tokyo Electron LimitedInventors: Makio Higashi, Akira Miyata
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Publication number: 20080020315Abstract: When a trouble occurs in a substrate treatment apparatus, the substrate existing in the substrate treatment apparatus is quickly collected without exerting adverse effects on the subsequent substrate treatment to resume the substrate treatment early. At the time of occurrence of trouble in a coating and developing treatment apparatus, all of the substrates in the coating and developing treatment apparatus are collected to a transfer-in/out section using a transfer unit in the apparatus. In this event, each transfer unit transfers the substrate from each position at the time of occurrence of trouble in a direction toward the transfer-in/out section for collection. Further, the substrate under treatment in the treatment unit at the time of occurrence of trouble is collected after the treatment is finished.Type: ApplicationFiled: June 23, 2005Publication date: January 24, 2008Applicant: Tokyo Electron LimitedInventors: Makio Higashi, Akira Miyata, Yoshitaka Hara
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Patent number: 7210864Abstract: A wafer flow recipe is prepared. Based on this wafer flow recipe, there are estimated and calculated respectively a PCD time from a time point at which a process for coating a resist liquid on a substrate by a coating unit has been terminated to a time point at which a first heating process is started at a first heating unit, a PAD time from a time point at which the first heating process has been terminated at the first heating unit to a time point at which an exposure process is started, and a PED time from a time point at which the exposure has been terminated to a time point at which a second heating process is started at a second heating unit. Then, these estimated times are displayed.Type: GrantFiled: January 4, 2005Date of Patent: May 1, 2007Assignee: Tokyo Electron LimitedInventors: Makio Higashi, Akira Miyata
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Patent number: 7191033Abstract: A substrate processing apparatus having a recipe storage section, a transfer control section and a transfer schedule changing section which, when delivery of an n-th substrate from a transfer art to the previous module is delayed by “m” cycles, changes a transfer schedule so as to move each of n-th and subsequent substrates (including the n-th substrate) in the transfer schedule to a module to which an “m”-th substrate following the substrate has been allocated, and transferring the changed transfer schedule data to the transfer control section.Type: GrantFiled: January 4, 2005Date of Patent: March 13, 2007Assignee: Tokyo Electron LimitedInventors: Makio Higashi, Akira Miyata
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Publication number: 20070016320Abstract: A substrate processing apparatus of the invention comprises a transfer schedule creating section, a transfer schedule storage section, a transfer control section which controls, by referring to the transfer schedule, plural transfer mechanisms so as to transfer a substrate written into data of a cycle containing plural transfer operations to a module corresponding to the substrate, and a standby position control section which operates such that, by referring to the transfer schedule stored in the transfer schedule storage section, after one transfer mechanism completes the transfer operations allotted to itself in one cycle, and during a period that another transfer mechanism executes the transfer operations allotted to itself in the one cycle, the standby position control section moves the one transfer mechanism and puts the one transfer mechanism on standby at a front module when viewed in the transfer operation in the modules allotted thereto in a next cycle.Type: ApplicationFiled: September 25, 2006Publication date: January 18, 2007Inventors: Makio Higashi, Akira Miyata
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Publication number: 20060011296Abstract: In the present invention, when a ghost wafer which is not recognized by a control unit on a coating and developing treatment apparatus side is carried out of another apparatus which is connected to the coating and developing treatment apparatus, the ghost wafer is temporarily housed in a buffer cassette on the coating and developing treatment apparatus side. The ghost wafer in the buffer cassette is then collected into a carry-in/out section on the coating and developing treatment apparatus side through use of a carrier unit at a timing which does not affect processing of other wafers According to the present invention, the ghost wafer occurred in the coating and developing treatment apparatus can be collected without suspension of processing of other ordinary substrates.Type: ApplicationFiled: July 12, 2005Publication date: January 19, 2006Inventors: Makio Higashi, Akira Miyata, Shinichi Seki
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Patent number: 6981808Abstract: A resist coating/developing system comprises a cassette station, a process station, and an interface station. A second wafer transfer member for transferring the wafer from a high precision temperature control unit mounted to the interface station to an in-stage of a light exposure device provisionally disposes the wafer held by the second wafer transfer member on a restoration unit in the case where the wafer was taken out from the high precision temperature control unit because it was possible to transfer the wafer onto the in-stage, but it was rendered impossible later to transfer the wafer W onto the in-stage.Type: GrantFiled: January 30, 2003Date of Patent: January 3, 2006Assignee: Tokyo Electron LimitedInventors: Akira Miyata, Makio Higashi, Shigeki Wada
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Publication number: 20050287821Abstract: In a coating and developing apparatus that forms a resist film on substrates such as semiconductor wafers, and develops substrates exposed by an aligner, times after the aligner unloads substrates until heating units (PEB) start heating the substrates are kept uniform. Exposed wafers are prevented from being left stagnant in an interface portion disposed between a region in which resist is coated and developed and the aligner. In the region in which resist is coated and developed, a first transferring means that successively executes transportation cycles to transfer substrates from upstream side modules to downstream side modules in a flow of processes of substrates. N heating units (PEB) are disposed (n is for example 5). Exposed wafers loaded into the heating units (PEB) are unloaded by the first transferring means after (n?1) cycles including the transferring cycle of the first transferring means have elapsed.Type: ApplicationFiled: November 18, 2003Publication date: December 29, 2005Inventors: Makio Higashi, Akira Miyata
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Publication number: 20050217581Abstract: A wafer flow recipe is prepared. Based on this wafer flow recipe, there are estimated and calculated respectively a PCD time from a time point at which a process for coating a resist liquid on a substrate by a coating unit has been terminated to a time point at which a first heating process is started at a first heating unit, a PAD time from a time point at which the first heating process has been terminated at the first heating unit to a time point at which an exposure process is started, and a PED time from a time point at which the exposure has been terminated to a time point at which a second heating process is started at a second heating unit. Then, these estimated times are displayed.Type: ApplicationFiled: January 4, 2005Publication date: October 6, 2005Inventors: Makio Higashi, Akira Miyata
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Publication number: 20050197729Abstract: A substrate processing apparatus comprising a recipe storage section, a transfer control section and a transfer schedule changing section which, when delivery of an n-th substrate from a transfer art to the previous module is delayed by “m” cycles, changes a transfer schedule so as to move each of n-th and subsequent substrates (including the n-th substrate) in the transfer schedule to a module to which an “m”-th substrate following the substrate has been allocated, and transferring the changed transfer schedule data to the transfer control section.Type: ApplicationFiled: January 4, 2005Publication date: September 8, 2005Inventors: Makio Higashi, Akira Miyata
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Publication number: 20030147643Abstract: A resist coating/developing system comprises a cassette station, a process station, and an interface station. A second wafer transfer member for transferring the wafer from a high precision temperature control unit mounted to the interface station to an in-stage of a light exposure device provisionally disposes the wafer held by the second wafer transfer member on a restoration unit in the case where the wafer was taken out from the high precision temperature control unit because it was possible to transfer the wafer onto the in-stage, but it was rendered impossible later to transfer the wafer W onto the in-stage.Type: ApplicationFiled: January 30, 2003Publication date: August 7, 2003Applicant: TOKYO ELECTRON LIMITEDInventors: Akira Miyata, Makio Higashi, Shigeki Wada