Patents by Inventor Makio Iida

Makio Iida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5592015
    Abstract: A semiconductor device is provided which makes a high withstand voltage bipolar transistor small and prevents deterioration in a switching speed of the transistor. A silicon oxide layer is formed on a silicon substrate, and a semiconductor island of one conductivity type which is isolated laterally by an isolation trench is formed on the silicon oxide layer. A silicon oxide film is formed on an outer periphery portion of the semiconductor island to bury the trench. In the semiconductor island, a bipolar transistor, namely a base region of the other conductivity type, is formed, and in the base region an emitter region of one conductivity type is formed and a collector region of one conductivity type is further formed. In the semiconductor island a diffusion region of the other conductivity type for extracting excessive carriers to which a constant electric potential is applied is further formed.
    Type: Grant
    Filed: October 26, 1995
    Date of Patent: January 7, 1997
    Assignee: Nippondenso Co., Ltd.
    Inventors: Makio Iida, Tadashi Shibata, Takayuki Sugisaka, Shoji Miura, Toshio Sakakibara
  • Patent number: 5557134
    Abstract: A dielectric isolated type semiconductor device which can achieve a reduction in crystalline defects by means of a simple production process is provided. High-concentration regions are formed as active regions on a surface portion of an islandish semiconductor region which is isolated from an adjacent semiconductor region by means of an isolation trench. According to a first aspect of the present invention, an N type crystalline defect suppression region doped at a high concentration and deeper than the high-concentration regions is formed over the entire surface of an adjacent semiconductor region. According to a second aspect of the present invention, a high-concentration N type crystalline defect suppression region is provided on a surface portion of a P type high-concentration region is formed with identical structure and by an identical production process. By means of these N type regions, crystalline defects are reduced.
    Type: Grant
    Filed: November 16, 1994
    Date of Patent: September 17, 1996
    Assignee: Nippondenso Co., Ltd.
    Inventors: Takayuki Sugisaka, Toshio Sakakibara, Shoji Miura, Makio Iida
  • Patent number: 5525831
    Abstract: A thin film resistor on a semiconductor device may be laser trimmed while reducing the influence of film thickness of a passivation film formed on the thin film resistor. An underlying oxide film consisting of a BPSG film and a silicon oxide film is formed on an Si substrate. A silicon oxide film and a silicon nitride film are formed on the underlying film as a passivation film, and a silicon oxide film is formed on this assembly. The silicon oxide film contributes to controlling a variation of the laser energy absorption rate of a thin film resistor due to an uneven thickness of the silicon nitride film. Thus, it is possible to stabilize adjustment of the resistance value of the thin film resistor with a laser.
    Type: Grant
    Filed: April 5, 1994
    Date of Patent: June 11, 1996
    Assignee: Nippondenso Co., Ltd.
    Inventors: Makoto Ohkawa, Makio Iida, Shoji Miura, Osamu Ishihara, Tetsuaki Kamiya
  • Patent number: 5503878
    Abstract: A method of preparing a patterned thin film resistor that is appropriately used in combination with semiconductor devices. The method comprises a thin film forming step comprising forming a thin film of a compound comprising at least one metal on an oxide film such as a silicon oxide film; a masking step comprising covering a desired area of the thin film by an organic material; a patterning step comprising converting to plasma a gas mixture comprising a fluorine compound gas and oxygen, and removing an area of the thin film, that is not covered by the organic material by exposing it to a gas containing activated fluorine by the plasma conversion; and a removing step comprising removing the organic material remaining on the desired area of the thin film.
    Type: Grant
    Filed: August 18, 1994
    Date of Patent: April 2, 1996
    Assignee: Nippondenso Co., Ltd.
    Inventors: Mikimasa Suzuki, Makio Iida, Makoto Muto
  • Patent number: 5449946
    Abstract: A semiconductor device is provided in which a contact is very simply formed on conductive material for capacitive coupling prevention. Two silicon substrates are bonded through a silicon oxide film. And a trench extending to the silicon oxide film is formed in one of silicon substrates so as to isolate between plural circuit elements from each other, and islands for circuit element formation are compartmently formed by the trench. A silicon oxide film is formed on an outer periphery portion of the islands for circuit element formation. Furthermore, an island for capacitive coupling prevention is formed by the silicon substrate between the islands for circuit element formation and is applied thereto to be maintained in an electric potential of constant.
    Type: Grant
    Filed: March 9, 1994
    Date of Patent: September 12, 1995
    Assignee: Nippondenso Co., Ltd.
    Inventors: Toshio Sakakibara, Makio Iida, Takayuki Sugisaka, Shoji Miura
  • Patent number: 5284794
    Abstract: A semiconductor device has a thin-film resistor trimmed by laser. The semiconductor device comprises a semiconductor substrate having an element region that covers at least part of the surface of the semiconductor substrate, a first insulation film disposed on the surface of the semiconductor substrate, and a second insulation film disposed on the surface of the semiconductor substrate through an opening of the first insulation film. The opening is formed by selectively removing at least part of the first insulation film at a location on the surface of the semiconductor substrate where the element region is not involved. The thin-film resistor is formed on the second insulation film.
    Type: Grant
    Filed: October 13, 1992
    Date of Patent: February 8, 1994
    Assignee: Nippondenso Co., Ltd.
    Inventors: Yoshihiko Isobe, Makio Iida, Shoji Miura, Keizou Kajiura, Mikimasa Suzuki, Masami Saito
  • Patent number: 5225286
    Abstract: A tantalum oxide dielectric film includes tantalum oxide (Ta.sub.2 O.sub.5) as a major component, and at least one oxide selected from the group consisting of yttrium oxide (Y.sub.2 O.sub.3), tungsten oxide (WO.sub.3) and niobium oxide (Nb.sub.2 O.sub.5). This dielectric film exhibits a remarkably improved dielectric constant and insulation property because it is a composite oxide film in which Ta.sub.2 O.sub.5 is compounded with Y.sub.2 O.sub.3, WO.sub.3 or Nb.sub.2 O.sub.5. For example, when the dielectric film is used as a capacitor film, the capacitor film exhibits a figure of merit, i.e., a product of a dielectric constant and an insulation property, approximately twice the silicon oxide (SiO.sub.2) film which is used widely for the purpose at present.
    Type: Grant
    Filed: June 12, 1992
    Date of Patent: July 6, 1993
    Assignees: Kabushiki Kaisha Toyota Chuo Kenkyusho, Nippondenso Co., Ltd.
    Inventors: Hisayoshi Fujikawa, Yasunori Taga, Makio Iida
  • Patent number: 5187559
    Abstract: A semiconductor device provided with a polycrystalline silicon resistor containing an impurity in a high concentration and having a resistance adjusted by a current conduction therethrough at a current density of a threshold value or more, which comprises: a polycrystalline silicon resistor containing a first impurity having a negative value of a temperature coefficient of resistance in a high impurity concentration region of said polycrystalline silicon resistor and a second impurity having a positive value of a temperature coefficient of resistance in a high impurity concentration region of the polycrystalline silicon resistor. A process for producing same is also disclosed.
    Type: Grant
    Filed: February 27, 1991
    Date of Patent: February 16, 1993
    Assignee: Nippondenso Co., Ltd.
    Inventors: Yoshihiko Isobe, Makio Iida