Patents by Inventor Makito Nakano

Makito Nakano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9536664
    Abstract: In an electronic component, capacitor conductors include linear portions parallel or substantially parallel to a lower surface of a laminate, and lead-out portions led out respectively from the linear portions to the lower surface. Outer electrodes are disposed on the lower surface and cover exposed portions where the lead-out portions are exposed at the lower surface, respectively. At least one of the linear portions includes a groove, which is recessed in a direction away from the lower surface, in a region thereof overlapping with the corresponding outer electrode when looking at the electronic component in a plan view from a z-axis direction.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: January 3, 2017
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Noriyuki Inoue, Mayuko Nishihara, Makito Nakano, Masayoshi Shimizu
  • Publication number: 20140029158
    Abstract: In an electronic component, capacitor conductors include linear portions parallel or substantially parallel to a lower surface of a laminate, and lead-out portions led out respectively from the linear portions to the lower surface. Outer electrodes are disposed on the lower surface and cover exposed portions where the lead-out portions are exposed at the lower surface, respectively. At least one of the linear portions includes a groove, which is recessed in a direction away from the lower surface, in a region thereof overlapping with the corresponding outer electrode when looking at the electronic component in a plan view from a z-axis direction.
    Type: Application
    Filed: October 4, 2013
    Publication date: January 30, 2014
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Noriyuki INOUE, Mayuko NISHIHARA, Makito NAKANO, Masayoshi SHIMIZU
  • Patent number: 7859822
    Abstract: A capacitor body includes a capacitance-forming section including an alternately arranged plurality of internal electrodes and plurality of dielectric ceramic layers and outer layer sections disposed on the upper or lower face of the capacitance-forming section (28). The outer layer sections include an outermost layer and a second layer (31) inwardly located therefrom. The second layer has a thermal expansion coefficient greater than that of the outermost layer by 1×10?6/° C. to 3×10?6/° C. The outermost layer has a thickness of 50 to 80 ?m. The second layer has a thickness of 20 to 50 ?m. The arrangement prevents cracks from being formed in a monolithic ceramic capacitor when external electrodes are formed by baking and cooling, and cracks caused by fatigue failure due to low-stress cycles such as heat cycles are prevented from reaching internal electrodes.
    Type: Grant
    Filed: August 14, 2007
    Date of Patent: December 28, 2010
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Makito Nakano, Akira Saito
  • Patent number: 7715172
    Abstract: A multilayer capacitor includes a capacitor body in which internal electrodes in a first internal electrode group are overlapped with internal electrodes in a second internal electrode group with dielectric layers sandwiched therebetween. A first external electrode has a first wraparound portion and a second wraparound portion, and a second external electrode has a third wraparound portion and a fourth wraparound portion. The volume proportions of the effective layers in a first area sandwiched between the first wraparound portion and the second wraparound portion and in a third area sandwiched between the third wraparound portion and the fourth wraparound portion are set to at least about 10%. The volume proportions of the effective layers in a second area toward a lower surface in the first area and in a fourth area toward the lower surface in the third area are set to about 15% or less. The external dimensions of the multilayer capacitor 1 are about 1.6±0.1 mm in length by about 0.8±0.
    Type: Grant
    Filed: July 11, 2008
    Date of Patent: May 11, 2010
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Kenichi Kawasaki, Noriyuki Inoue, Akira Saito, Makito Nakano, Kenichi Oshiumi
  • Patent number: 7715171
    Abstract: The “squeal” that occurs when an electric field is applied to a multilayer ceramic capacitor mounted on a substrate is suppressed by providing in an active part contributing to formation of capacitances between internal electrodes facing each other in a capacitor body, low-activity regions positioned near respective end edges of respective external electrodes. A facing area of the internal electrodes in the low-activity regions is less than or equal to one fifth that of the internal electrodes in a normal region having the same volume as that of the low-activity regions. This makes it possible to suppress occurrence of electric-field-induced distortion near the external electrodes bonded to a substrate and reduce the force that causes the substrate to bend.
    Type: Grant
    Filed: January 30, 2008
    Date of Patent: May 11, 2010
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Makito Nakano, Noriyuki Inoue, Kenichi Kawasaki
  • Publication number: 20090002918
    Abstract: A multilayer capacitor includes a capacitor body in which internal electrodes in a first internal electrode group are overlapped with internal electrodes in a second internal electrode group with dielectric layers sandwiched therebetween. A first external electrode has a first wraparound portion and a second wraparound portion, and a second external electrode has a third wraparound portion and a fourth wraparound portion. The volume proportions of the effective layers in a first area sandwiched between the first wraparound portion and the second wraparound portion and in a third area sandwiched between the third wraparound portion and the fourth wraparound portion are set to at least about 10%. The volume proportions of the effective layers in a second area toward a lower surface in the first area and in a fourth area toward the lower surface in the third area are set to about 15% or less. The external dimensions of the multilayer capacitor 1 are about 1.6±0.1 mm in length by about 0.8±0.
    Type: Application
    Filed: July 11, 2008
    Publication date: January 1, 2009
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Kenichi KAWASAKI, Noriyuki INOUE, Akira SAITO, Makito NAKANO, Kenichi OSHIUMI
  • Publication number: 20080130198
    Abstract: The “squeal” that occurs when an electric field is applied to a multilayer ceramic capacitor mounted on a substrate is suppressed by providing in an active part contributing to formation of capacitances between internal electrodes facing each other in a capacitor body, low-activity regions positioned near respective end edges of respective external electrodes. A facing area of the internal electrodes in the low-activity regions is less than or equal to one fifth that of the internal electrodes in a normal region having the same volume as that of the low-activity regions. This makes it possible to suppress occurrence of electric-field-induced distortion near the external electrodes bonded to a substrate and reduce the force that causes the substrate to bend.
    Type: Application
    Filed: January 30, 2008
    Publication date: June 5, 2008
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Makito NAKANO, Noriyuki INOUE, Kenichi KAWASAKI
  • Publication number: 20080013252
    Abstract: A capacitor body includes a capacitance-forming section including an alternately arranged plurality of internal electrodes and plurality of dielectric ceramic layers and outer layer sections disposed on the upper or lower face of the capacitance-forming section (28). The outer layer sections include an outermost layer and a second layer (31) inwardly located therefrom. The second layer has a thermal expansion coefficient greater than that of the outermost layer by 1×10?6/° C. to 3×10?6/° C. The outermost layer has a thickness of 50 to 80 ?m. The second layer has a thickness of 20 to 50 ?m. The arrangement prevents cracks from being formed in a monolithic ceramic capacitor when external electrodes are formed by baking and cooling, and cracks caused by fatigue failure due to low-stress cycles such as heat cycles are prevented from reaching internal electrodes.
    Type: Application
    Filed: August 14, 2007
    Publication date: January 17, 2008
    Applicant: MURATA MANUFACTURING CO., LTD.
    Inventors: Makito Nakano, Akira Saito