Abstract: A first phase comparator 22 of digital type and a second phase comparator 32 of sampling type are provided. Near a lock phase, an output current Iout2 is fed from the second phase comparator 32 to a voltage-controlled oscillator 14 through a change-over switch 40. In other phases, an output current Iout1 is fed thereto from the first phase comparator 22. When a reference signal fs is missing, a complementing circuit 50 complements a pulse to at least the reference signal fs input to the first phase comparator 22. A noise detecting/removing circuit 60 detects and removes noise from the reference signals fs, permits the reference signals fs to be fed to the first and second phase comparators 22 and 23, and halts the operations of the two phase comparators 22 and 32 for only a predetermined period of time after the noise has been detected.

Abstract: A first reproduced color under signal is delayed by one or two horizontal periods by a delay circuit, and this delayed second reproduced color under signal and the aforementioned first reproduced color under signal have their frequencies converted individually by first and second frequency converters into standard color signals. An oscillatory frequency signals of 2n of carriers for the aforementioned frequency conversions are divided to have the aforementioned carrier frequencies and to produce four carriers having phases of 0, 90, 180 and 270 degrees. These carriers are selectively fed to the first and second frequency converters by switches so that the two frequency-converted signals are subtracted or added in phase or in opposite phase to clear the noise (or crosstalk component), which is caused by the crosstalk between the tracks.

Abstract: A video signal processing device comprises: a unit for extracting a first color burst signal from a first video signal; a unit for generating a first subcarrier in synchronism with the first color burst signal extracted from the first video signal; a unit for extracting a second chrominance signal and a second color burst signal from a second video signal; a unit for demodulating the second chrominance signal and the second color burst signal on the basis of the first subcarrier to obtain a demodulated second color signal and a demodulated second color burst signal; and an operating unit for performing operation process of the demodulated second color signal on the basis of the demodulated second color burst signal in a manner such that the demodulated second color signal is converted into a corrected color signal which is substantially the same as an imaginal second color signal which is obtained on the assumption that the second chrominance signal is demodulated on the basis of a second subcarrier synchroni

Abstract: Disclosed is a novel semiconductor integrated circuit device for use in a color VTR (Video Tape Recorder). Concretely, the semiconductor integrated circuit device comprises a substantially rectangular semiconductor chip which has a principal surface, a luminance signal processing unit and a color signal processing unit which are disposed at the positions of the principal surface opposing to each other, and a semiconductor region which is provided in the interspace of the principal surface between the luminance signal and color signal processing units opposing to each other and which is supplied with a bias stable A.C.-wise. Further, the semiconductor region is located substantially at the central portion of the semiconductor chip and is extended so as to intersect with one set of opposing sides of the rectangular semiconductor chip.

Abstract: In a case where an electronic circuit having the same function is to be realized by a different device, it is indispensable to prepare circuit diagrams conforming to devices and to utilize them for the job of circuit simulation or chip layout. When the circuit diagrams are to be automatically translated for the above purpose, translation rules become different depending upon the connective relations of an element to be translated, with other elements in the circuit or upon a function performed by the element. The present invention puts the rules into knowledge from the viewpoint of knowledge engineering and utilizes it thereby to realize the intended purpose.

Abstract: A semiconductor integrated circuit device comprising a logic circuit which is constituted by using tri-state IIL gates. The tri-state IIL gates are particularly arranged to have first and second inputs. If the second input has a first level, the circuit will operate as a normal IIL circuit to provide high and low outputs in response to the first input. However, if the second input has a second level, the circuit will provide a floating output regardless of the first input. The transistors of the IIL circuit can be formed in an island in the substrate, with the potential of the island serving as the second input. In a preferred arrangement, the first level of the second input can be obtained by grounding the island while the second level is obtained by disconnecting the island from ground. These tri-state IIL gates are particularly advantageous to form a transfer gate for an IIL memory similar to the transfer gates used for MOS memories. They can also be used for forming various other logic gate arrangements.

Abstract: In order to translate an original circuit consisting of a set of first devices into a target circuit which consists of a set of second devices different from the first devices, and which has the same functions as the original circuit, provision is made of memory means for storing translation rules in the first devices, translation rules in the second devices, and translation rules between the first devices and the second devices, and translation means which successively refers to these translation rules and translates the original circuit data into the target circuit data via steps that translate the original circuit data into a plurality of intermediate data.

Abstract: An integrated programmable logic array formed within a single silicon chip comprises a combination of a logical product gate array and a logical summation gate array. The logical product gate array is equipped with a plurality of MIS field-effect transistors whose gates are selectively driven by a plurality of input signals. Source-drain paths of these transistors are connected in series. The logical summation gate array is equipped with a plurality of inverted bipolar transistors having collector-emitter paths which are connected in parallel.

Abstract: A logic circuit is provided which includes a first multi-emitter transistor with its emitters coupled to a group of first input lines and a first transistor with its base coupled to the collector of said first multi-emitter transistor. A second transistor is also provided with its base coupled to the collector of said first transistor, said second transistor having a polarity opposite to that of said first multi-emitter transistor. A second multi-emitter transistor is connected with its base coupled to the collector of said second transistor and with its emitters coupled to a group of second input lines, and a third transistor is connected with its base coupled to the collector of said second multi-emitter transistor and with its collector coupled to an output line. The collector of said first multi-emitter transistor is coupled to the emitter of said second multi-emitter transistor in order to absorb minority carriers stored in the transistors. This feature significantly improves the circuit operating speed.

Abstract: A logic circuit of a large scale which consumes small amounts of electric power is comprised of a plurality of ROM portions each formed of IIL circuits. Input signal lines are commonly used to transmit input signals to the ROM portions. The plurality of ROM portions are selectively operated by ROM select signals, and outputs corresponding to the input signals are obtained from a selected ROM portion. To select a particular ROM portion out of the plurality of ROM portions, the emitters of inverse npn transistors of IIL circuits constituting the selected ROM portion are rendered to assume ground potential. In the meantime, the emitters of the inverse npn transistors of IIL circuits in the non-selected ROM portions are held in a floating condition. This makes it possible to obtain a logic circuit which consumes small amounts of electric power with a very simple construction since the non-selected ROM portions consume no power.

Abstract: An integrated programmable logic array formed within a single silicon chip comprises a combination of an NAND or AND gate array and an NOR or OR gate array.The NAND or AND gate array includes a plurality of bipolar transistors which are driven to operate in the forward direction by a plurality of input signals, and a plurality of Schottky barrier diodes provided between the collectors of the bipolar transistors and output signal lines. The NOR or OR gate array includes a plurality of other bipolar transistors which are driven to operate in the backward direction by a plurality of output signals from the NAND or AND gate array.

Abstract: A semiconductor integrated circuit includes low voltage operation circuitries such as I.sup.2 L and high voltage operation circuitries operating at a higher voltage than the low voltage operation circuitries. Both of the low and high voltage operation circuitries are implemented in a single semiconductor chip in coexistence with each other. The low voltage operation circuitries are disposed in constant current paths in the high voltage operation circuitries so that the currents once used by the high voltage operation circuits are utilized again by the low voltage operation circuitries. Power dissipation of the whole integrated circuit is thus reduced significantly.

Abstract: A parallel comparator includes a plurality of comparator portions each having first and second transistors differentially connected. The first transistors have their bases connected to receive an analog input signal, whereas the second transistors have their bases connected to receive reference voltages having different levels. Among the plural comparator portions, the collector of the first transistor and the collector of the second transistor are connected with a load in accordance to a predetermined rule. An A/D converter for converting an analog input signal into digital signals of plural codes is also provided which includes a critical detecting comparator for generating a detection output at a predetermined level when the digital signals of the plural codes are converted into such an analog signal as effects the overflow or underflow.

Abstract: A frequency modulation detector is constructed of a plurality of monostable multivibrators, an analog and a low-pass filter. One of the plurality of monostable multivibrators generates a first train of pulses of predetermined pulse width in response to the rising edges of an input signal, while another of the plurality of monostable multivibrators generates a second train of pulses of the same predetermined pulse width in response to the falling edges of the input signal. The first and second trains of pulses are applied to the analog adder, an output signal of which is applied to an input terminal of the low-pass filter. An FM detection output signal is provided from an output terminal of the low-pass filter. By this means the high-frequency components and carrier components of the input to be contained in the FM detection output signal are substantially reduced.

Abstract: A discriminator apparatus for a television multivoice system comprises a mixer for mixing a program identifying signal with a reference signal thereby to produce a differential beat signal. A reference signal generator includes a signal source of an original frequency, and a frequency converter for converting the original frequency to the reference frequency which is close to the frequency of the program identifying signal and so selected that the frequency of the differential beat signal is lower than the lowest audible frequency. A low-pass filter is employed for extracting the differential beat signal. Need for expensive mechanical filters of a narrow fractional bandwidth is thereby eliminated.

Abstract: A chroma signal gain control circuit is constructed to include a first band pass amplifier, a second band pass amplifier, a burst gate circuit, a switch circuit and an ACC detecting circuit. The output signal of the first band pass amplifier is fed to the input of the second band pass amplifier, the output signal of which is fed to the input of the burst gate circuit. The switch circuit selectively transmits either the output of the burst gate circuit or the output of the second band pass amplifier to the ACC detecting circuit. The gain of the first band pass amplifier is controlled by feeding the detected output of the ACC detecting circuit to the first band pass amplifier. In order to prevent over-saturation in case the level ratio (C/B) between the color burst signal and the chroma signal exceeds a predetermined value, the switch circuit will selectively transmit the output of the second band pass amplifier to the ACC detecting circuit.

Abstract: A synchronizing signal generator device for television includes an oscillator circuit which generates a color subcarrier signal, a voltage-controlled oscillator circuit which includes a counter and whose oscillation frequency is controlled by the output signal of the first-mentioned oscillator circuit, a counter which receives an output of the voltage-controlled oscillator circuit, and a decoder which receives an output of the second-mentioned counter. The decoder provides a synchronizing signal for the NTSC, PAL or SECAM format in such a manner that the count numbers of the respective counters are controlled. The synchronizing signal generator device for television also includes various circuits for receiving external synchronizing signals. As a result, the synchronizing signal generator device for television can be synchronized with another synchronizing signal generator device for television.

Abstract: A phase control circuit includes a controlled voltage source circuit and a controlled current source circuit receiving a reference frequency signal, a first impedor connected between the controlled voltage source circuit and an output terminal of the phase control circuit, a second impedor connected between a DC power source and the output terminal, and an output control circuit connected between the output terminal and the controlled current source circuit. The oscillator circuit comprises a crystal oscillator, a circuit for amplifying the output of the oscillator and a circuit arrangement almost similar to the phase control circuit in which the reference frequency signal is supplied from the crystal oscillator. The phase control circuit and the oscillator circuit are suited for an integrated circuit construction.

Abstract: In a synchronizing detector circuit which has at least two differential transistors, a pair of constant current transistors are connected to the differential transistors, and an output transistor is connected to the junctures between the differential and constant current transistors and to a filter circuit for detection. A synchronizing detector circuit comprises a compensating circuit incorporated between the junctures and the filter circuit and includes a constant current absorbing circuit, so as to prevent an offset output voltage of the filter circuit due to noise.