Abstract: A method monitors an air-conditioner having a semi-conductor gas sensor, the method including: determining that a refrigerant leakage has occurred on condition that the detection value is equal to or greater than a first threshold when the fan is in operation; starting operation of the fan as a provisional operation if the detection value is equal to or greater than a second threshold when the fan is not in operation; stopping the provisional operation of the fan; determining that a refrigerant leakage has occurred on condition that the detection value is equal to or greater than a third threshold after stopping the provisional operation of the fan; and taking a predetermined action for outputting alarm information and/or limiting supply of refrigerant to the heat exchanger when a refrigerant leakage is determined to have occurred.

Abstract: There are provided a cell aggregate that can be used as a cell preparation in regenerative medicine, maintains the original characteristics of cells, and has high safety, and a method for simply and safely maintaining the cell aggregate size, the cell characteristics and viability suitable for use as a cell preparation in regenerative medicine. According to an aspect of the present invention, a cell aggregate maintaining method is a method including a maintenance process of maintaining a liquid containing a plurality of the cell aggregates at a temperature which is lower than a culture temperature of the cells and at which the liquid is not frozen.

Abstract: A display device is a display device provided with a display region including a plurality of pixels and a frame region surrounding the display region, and includes: a thin film transistor layer; and a light-emitting element layer including a plurality of light-emitting elements, each including a first electrode, a function layer, and a second electrode, and each having a different luminescent color, wherein the function layer includes a light-emitting layer, and a pair of holding layers sandwiching the light-emitting layer and each including a photosensitive material and a conductive nanoparticle.

Abstract: A method of manufacturing a display device includes: a) a step of preparing a substrate including an electrode and another electrode; b) a step of forming a photosensitive resin material layer on the substrate; c) a step of forming a charge transport material layer and a light-emitting material layer on the substrate; and d) a step of patterning the photosensitive resin material layer, the charge transport material layer, and the light-emitting material layer into a photosensitive resin layer, a charge transport layer, and a light-emitting layer respectively by retaining, without lifting off, non-lift-off portions of the photosensitive resin material layer, the charge transport material layer, and the light-emitting material layer, the non-lift-off portions being provided at least on a part of the electrode, and lifting off lift-off portions of the photosensitive resin material layer, the charge transport material layer, and the light-emitting material layer.

Abstract: Methods, systems, and devices for power gating in a memory device are described for using one or more memory cells as drivers for load circuits of a memory device. A group of memory cells of the memory device may represent memory cells that include a switching component and that omit a memory storage element. These memory cells may be coupled with respective plate lines that may be coupled with a voltage source having a first supply voltage. Each memory cell of the group may also be coupled with a respective digit line that may be coupled with the load circuits. Respective switching components of the group of memory cells may therefore act as drivers to apply the first supply voltage to one or more load circuits by coupling a digit line with a plate line having the first supply voltage.

Abstract: A method of performing a memory cell operation can include maintaining a plate voltage at a first access line of a memory cell during at least a first operation and a second operation of the memory cell. The method can further include charging a second access line to a first voltage greater than zero and greater than a threshold voltage of a selector device of the memory cell during the first operation on the memory cell. The method can further include, subsequent to the first operation, charging the second access line to a second voltage greater than the plate voltage plus the threshold voltage of the selector device to perform the second operation of the memory cell.

Abstract: A light-emitting element producing method includes: a step of forming a first-charge transport layer on a first electrode; a step of applying a first photosensitive resin composition, containing first quantum dots, to the first-charge transport layer, and forming a first-quantum-dot containing layer; a step of applying a second photosensitive resin composition, containing second quantum dots, to the first-quantum-dot containing layer, and forming a second-quantum-dot containing layer; a step of forming a second-charge transport layer on the second-quantum-dot containing layer; and a step of forming a second electrode on the second-charge transport layer.

Abstract: Memory systems and memory programming methods are described.

Abstract: Ferroelectric memory arrays with reduced current leakage is described herein. A ferroelectric memory array may include a number of memory cells including capacitors with ferroelectric material. Providing an intermediary word line voltage to non-selected word lines that are not electrically coupled to a target memory cell during a sensing operation may reduce leakage current from an active data line electrically coupled to the target memory cell to the non-selected word lines. The intermediary word line voltage may be provided using an amplitude between an idle voltage of the data lines and zero volts. The intermediary word line voltage may be reduced closer to zero volts for performing a programming operation.

Abstract: Methods, systems, and devices for sense timing coordination are described. In some systems, to sense the logic states of memory cells, a memory device may generate an activation signal and route the activation signal over a signal line (e.g., a dummy word line) located at a memory array level of the memory device to one or more sense amplifiers. Based on receiving the activation signal, a sense amplifier may latch and determine the logic state of a corresponding memory cell. A first sense amplifier may sense a state of a first memory cell at a first time and a second sense amplifier may sense a state of a second memory cell at a second time in response to the same activation signal due to a propagation delay of the activation signal routed over the signal line (e.g., and corresponding to a propagation delay for activating a word line).

Abstract: Methods, systems, and devices for power gating in a memory device are described for using one or more memory cells as drivers for load circuits of a memory device. A group of memory cells of the memory device may represent memory cells that include a switching component and that omit a memory storage element. These memory cells may be coupled with respective plate lines that may be coupled with a voltage source having a first supply voltage. Each memory cell of the group may also be coupled with a respective digit line that may be coupled with the load circuits. Respective switching components of the group of memory cells may therefore act as drivers to apply the first supply voltage to one or more load circuits by coupling a digit line with a plate line having the first supply voltage.

Abstract: A display device includes a thin film transistor layer, a light-emitting element layer including a plurality of light-emitting elements, each including a first electrode, a function layer, and a second electrode, and each having a different luminescent color. The function layer includes a light-emitting layer and a pair of holding layers sandwiching the light-emitting layer and each including a photosensitive material. One of the first electrode and the second electrode is an anode electrode and the other is a cathode electrode. The function layer includes a hole transport layer provided between the anode electrode and one holding layer of the pair of holding layers, and an electron transport layer provided between the cathode electrode and the other holding layer of the pair of holding layers.

Abstract: Methods, systems, and devices for sense timing coordination are described. In some systems, to sense the logic states of memory cells, a memory device may generate an activation signal and route the activation signal over a signal line (e.g., a dummy word line) located at a memory array level of the memory device to one or more sense amplifiers. Based on receiving the activation signal, a sense amplifier may latch and determine the logic state of a corresponding memory cell. A first sense amplifier may sense a state of a first memory cell at a first time and a second sense amplifier may sense a state of a second memory cell at a second time in response to the same activation signal due to a propagation delay of the activation signal routed over the signal line (e.g., and corresponding to a propagation delay for activating a word line).

Abstract: Methods, systems, and devices for power gating in a memory device are described for using one or more memory cells as drivers for load circuits of a memory device. A group of memory cells of the memory device may represent memory cells that include a switching component and that omit a memory storage element. These memory cells may be coupled with respective plate lines that may be coupled with a voltage source having a first supply voltage. Each memory cell of the group may also be coupled with a respective digit line that may be coupled with the load circuits. Respective switching components of the group of memory cells may therefore act as drivers to apply the first supply voltage to one or more load circuits by coupling a digit line with a plate line having the first supply voltage.

Abstract: Methods, systems, and devices for power gating in a memory device are described for using one or more memory cells as drivers for load circuits of a memory device. A group of memory cells of the memory device may represent memory cells that include a switching component and that omit a memory storage element. These memory cells may be coupled with respective plate lines that may be coupled with a voltage source having a first supply voltage. Each memory cell of the group may also be coupled with a respective digit line that may be coupled with the load circuits. Respective switching components of the group of memory cells may therefore act as drivers to apply the first supply voltage to one or more load circuits by coupling a digit line with a plate line having the first supply voltage.

Abstract: Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with the common conductor. The memory system additionally includes access circuitry configured to provide different ones of the memory cells into one of a plurality of different memory states at a plurality of different moments in time between first and second moments in time. The access circuitry is further configured to maintain the common conductor at a voltage potential, which corresponds to the one memory state, between the first and second moments in time to provide the memory cells into the one memory state.

Abstract: A memory apparatus includes a memory cell disposed at an intersection of a first wiring line and a second wiring line, and including a variable resistor and a selector, the variable resistor having a resistance state that changes to a first resistance state and a second resistance state, and a drive circuit that writes data to the memory cell by changing the variable resistor from the first resistance state to the second resistance state, and erases the data stored in the memory cell by changing the variable resistor from the second resistance state to the first resistance state. When erasing the data, the drive circuit changing in a stepwise manner a voltage applied to the memory cell, and changing in a stepwise manner a current limit value that limits a magnitude of a current flowing through the memory cell.

Abstract: In a memory unit according to an embodiment of the present disclosure, a memory cell array is configured, when, of a plurality of memory cells, multiple first memory cells whose corresponding fourth wiring line and first wiring line are different from one another are simultaneously accessed, to allow for simultaneous access to the multiple first memory cells, without allowing for simultaneous access to memory cells corresponding to the fourth wiring line shared by the first memory cells.

Abstract: A storage device according to the present disclosure includes: a plurality of first wiring lines extending in a first direction and including a plurality of first selection lines and a plurality of second selection lines; a plurality of second wiring lines extending in a second direction and including a plurality of third selection lines and a plurality of fourth selection lines, the second direction intersecting the first direction; a plurality of first memory cells; a first driver including a first selection line driver that drives the plurality of first selection lines on a basis of a first selection control signal and a second selection line driver that drives the plurality of second selection lines on a basis of the first selection control signal, the first and second selection line drivers being arranged side-by-side in the first direction; and a second driver including a third selection line driver that drives the plurality of third selection lines on a basis of a second selection control signal and a

Abstract: Memory systems and memory programming methods are described. According to one aspect, a memory system includes program circuitry configured to provide a program signal to a memory cell to program the memory cell from a first memory state to a second memory state, detection circuitry configured to detect the memory cell changing from the first memory state to the second memory state during the provision of the program signal to the memory cell to program the memory cell, and wherein the program circuitry is configured to alter the program signal as a result of the detection and to provide the altered program signal to the memory cell to continue to program the memory cell from the first memory state to the second memory state.