Abstract: A lateral short-channel DMOS includes an epitaxial layer formed on a semiconductor substrate. A first conductivity-type well is formed in the epitaxial layer. A second conductivity-type well is formed in the first conductivity-type well and includes a channel forming region. A source region is formed in the second conductivity-type well. A first conductivity-type ON resistance lowering well is formed in the epitaxial layer so as to contact the first conductivity-type well but not the second conductivity-type well, and includes a higher concentration of a first conductivity-type dopant than the first conductivity-type well. A drain region is formed in the first conductivity-type ON resistance lowering well. A gate electrode is formed above and insulated from at least the channel forming region.

Abstract: A lateral short-channel DMOS includes an N?-type epitaxial layer 110 in a P?-type semiconductor substrate 108, a P-type well 114 in the N?-type epitaxial layer 110 with a channel forming region C, an N+-type source region 116 in the P-type well 114, an N+-type drain region 118 in N?-type epitaxial layer 110, and a gate electrode 122 formed via a gate insulating film 120 in at least an upper part of the channel forming region C out of a region from the N+-type source region 116 to the N+-type drain region 118. The lateral short-channel DMOS also includes an N+-type well 140 that is formed in the N?-type epitaxial layer 110 and includes a concentration of N-type dopant higher than the N?-type epitaxial layer 110 and lower than the N+-type drain region 118, with the N+-type drain region 118 being formed in this N+-type well 140.

Abstract: A lateral short-channel DMOS according to the present invention is a lateral short-channel DMOS in which an N?-type semiconductor region is formed, with the surface of the N?-type semiconductor region becoming almost completely depleted during reverse bias. The lateral short-channel DMOS 10A according to the present invention includes an N?-type epitaxial layer 110 that is formed in one surface of a P?-type semiconductor substrate 108, a P-type well 114 that is formed in the surface of the N?-type epitaxial layer 110 and includes a channel forming region C, an N+-type source region 116 that is formed in a surface of the P-type well 114, an N+-type drain region 118 formed in a surface of the N?-type epitaxial layer 110, and a gate electrode 122 formed via a gate insulating film 120 in at least an upper part of the channel forming region C out of a region from the N+-type source region 116 to the N+-type drain region 118.

Abstract: A lateral short-channel DMOS 10A according to the present invention includes an N−-type epitaxial layer 110 formed on a surface of a P−-type semiconductor substrate 108, a P-type well 114 that is formed in a surface of the N−-type epitaxial layer 110 and includes a channel forming region C, an N+-type source region 116 formed in a surface of the P-type well 114, an ON resistance lowering N-type well 134 formed in a surface of the N−-type epitaxial layer 110 so as to not contact the P-type well 114, an N+-type drain region 118 formed in a surface of the ON resistance lowering N-type well 134, a polysilicon gate electrode 122 formed via a gate insulating film 120 in at least an upper part of the channel forming region C out of a region from the N+-type source region 116 to the N+-type drain region 118, and a gate resistance lowering metal layer 130 connected to the polysilicon gate electrode 122.