Abstract: There is disclosed a vertical deflection circuit for use in a display device employing a CRT. The vertical deflection circuit has a DSP (digital signal processor) for producing a digital current signal during each main period. This digital current signal shows plural current values which increases in first equal increments from a different value during each main period. The digital current value is converted into an analog current signal by a D/A converter and then averaged by a low-pass filter. A vertical deflection current is produced based on the averaged analog current signal. Because plural different current values are averaged, the average value varies linearly. Accordingly, the vertical deflection current varies linearly with each main period.

Abstract: There is disclosed a vertical deflection circuit for use in a display device employing a CRT. The vertical deflection circuit has a DSP (digital signal processor) for producing a digital current signal during each main period. This digital current signal shows plural current values which increases in first equal increments from a different value during each main period. The digital current value is converted into an analog current signal by a D/A converter and then averaged by a low-pass filter. A vertical deflection current is produced based on the averaged analog current signal. Because plural different current values are averaged, the average value varies linearly. Accordingly, the vertical deflection current varies linearly with each main period.

Abstract: The bit stream reproducing apparatus is comprised of a frame length counter for measuring a data length of one frame; a first calculator for calculating a data length “L1” defined from a header to a scale factor; a second calculator for calculating a data length “L2” of an audio sample; and a third calculator for executing a calculation of E=F−(L1+L2×12) based upon calculation results of the first calculator and of the second calculator, and for sending out a control signal to a muting circuit so as to instruct a muting operation in the case of E<0.

Abstract: A magnetic recording and reproduction apparatus wherein the drum motor is controlled so that the rotation number of the drum during playback at the normal speed multiplied by N (N is an integer) changes by a fixed factor to R(1+q/Q) (Q, q are integers satisfying .vertline.q.vertline.<.vertline.Q.vertline.), assuming the rotation number of the drum during normal playback as R rpm. Also a magnetic recording and reproduction apparatus wherein the drum motor is controlled so that the average rotation number of the drum during playback at the normal speed multiplied by N (N is an integer) becomes approximately R rpm by changing the rotation number of the drum periodically and combining a rotation number of R rpm or less and a rotation number of R rpm or more, assuming the rotation number of the drum during normal playback as R rpm.

Abstract: A digital video signal recording and reproducing apparatus which obtains a favorable reproduced picture even when the data overwritten by edited data is interpolated with the data of the preceding field or preceding frame by recording the video data of the visually inconspicuous peripheral area on a track that is possibly overwritten by the editing data at a cut-in point or cut-out point in assemble editing or insert editing. The apparatus further obtains a natural picture without any fixed error even in speed search mode by exchanging the recording order of the video data of one field on plural tracks according to the head scanning trace in the speed search.

Abstract: When recording HD video signals, twice the number of tracks are used as compared to recording the conventional NTSC video signals, and video signals are recorded in the audio sector. HD video signals are encoded with the same number of checks as the error-correcting code of the present video signals, with the number of information symbols being increased. When recording HD video signals and present video signals, these signals are encoded so that the shortest recording wavelength is the same with either signal.

Abstract: In an error-correcting apparatus for correcting errors included in reproduced data which are stored in a RAM, a syndrome generation circuit, a polynomial calculation circuit for calculating an error position polynomial and an error value polynomial, and a position calculation circuit for calculating an error position are operated in parallel. A divider section of the error-correcting apparatus has a divider for performing the division of highest-degree coefficients of two polynomials, a multiplier for multiplying the coefficient of the polynomial set in the divisor side of the divider by the output of the divider, and an adder for adding the output of the multiplier and the coefficient of the polynomial set in the dividend side of the divider. The divider section executes the division over a Galois field while sequentially shifting the contents of registers which store the coefficient data of the dividend polynomial.

Abstract: In an error-correcting apparatus for correcting errors included in reproduced data which are stored in a RAM, a syndrome generation circuit, a polynomial calculation circuit for calculating an error position polynomial and an error value polynomial, and a position calculation circuit for calculating an error position are operated in parallel. A divider section of the error-correcting apparatus has a divider for performing the division of highest-degree coefficients of two polynomials, a multiplier for multiplying the coefficient of the polynomial set in the divisor side of the divider by the output of the divider, and an adder for adding the output of the multiplier and the coefficient of the polynomial set in the dividend side of the divider. The divider section executes the division over a Galois field while sequentially shifting the contents of registers which store the coefficient data of the dividend polynomial.

Abstract: Specified modular arithmetic is applied to input digital data to divide the input data into two main codes and a subcode. Otherwise, input digital data is divided into two pieces of digital data according to a specified rule. The digital data is divided so that the original input digital data can be completely restored if the two main codes and the subcode or both of the divided data are used, and the original input digital data can be nearly correctly restored even when one of the main codes or one of the divided data is used.

Abstract: A video signal processing apparatus which includes a clock signal generator for generating a clock signal in synchronism with a color synchronizing signal contained in an incoming video signal. This clock signal has a frequency equal to a multiple of the frequency of the color synchronizing signal. An analog-to-digital converter operates in response to the clock signal to sample and convert an incoming composite video signal into a digital video signal. An address setting circuit is provided for generating an address signal synchronized with horizontal and vertical synchronizing signals.