Patents by Inventor Makoto Kuribara
Makoto Kuribara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230315312Abstract: A memory system includes a non-volatile memory including a first memory cell unit and a second memory cell unit, and a controller connectable to a host. The controller is configured to store an execution time of write and erase operations with respect to the first memory cell unit, receive from the host power-on time information indicating a power-on time of the memory system when the memory system is powered on, determine a first time period from a last write or erase operation with respect to the first memory cell unit based on the stored execution time and the power-on time, determine an execution time of a refresh operation of transferring data stored in the first memory cell unit to the second memory cell unit based on the first time period, and start the refresh operation at the determined execution time.Type: ApplicationFiled: August 30, 2022Publication date: October 5, 2023Inventors: Kenji TAKAHASHI, Makoto KURIBARA, Shin TAKASAKA, Rintaro ARAI
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Patent number: 11581046Abstract: According to one embodiment, a storage device includes a nonvolatile memory and a controller. The controller is configured to read data from the nonvolatile memory by applying a read voltage to the nonvolatile memory. The controller is configured to correct the read voltage based on a difference between a measured value of a bit number obtained when the data is read from the nonvolatile memory by applying the read voltage to the nonvolatile memory and an expected value of the bit number.Type: GrantFiled: March 15, 2021Date of Patent: February 14, 2023Assignee: Kioxia CorporationInventors: Makoto Kuribara, Shin Takasaka, Rintaro Arai
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Patent number: 11581052Abstract: According to one embodiment, a memory system includes a non-volatile memory and a controller. The memory includes a plurality of storage areas. Each of the storage areas includes a plurality of memory cells to which threshold voltages are set in accordance with data. The controller acquires a first threshold voltage distribution of memory cells in a first storage area of the storage areas. The controller acquires a second threshold voltage distribution of memory cells in a second storage area of the storage areas. The controller detects non-normalcy in the first storage area or the second storage area from a first divergence quantity between the first threshold voltage distribution and the second threshold voltage distribution.Type: GrantFiled: September 3, 2020Date of Patent: February 14, 2023Assignee: Kioxia CorporationInventors: Akiyoshi Hashimoto, Makoto Kuribara, Takeshi Tomizawa, Katsuhiko Ueki
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Publication number: 20220093182Abstract: According to one embodiment, a storage device includes a nonvolatile memory and a controller. The controller is configured to read data from the nonvolatile memory by applying a read voltage to the nonvolatile memory. The controller is configured to correct the read voltage based on a difference between a measured value of a bit number obtained when the data is read from the nonvolatile memory by applying the read voltage to the nonvolatile memory and an expected value of the bit number.Type: ApplicationFiled: March 15, 2021Publication date: March 24, 2022Applicant: Kioxia CorporationInventors: Makoto KURIBARA, Shin TAKASAKA, Rintaro ARAI
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Patent number: 11138070Abstract: According to one embodiment, a memory system includes a non-volatile semiconductor memory having a plurality of blocks each including a plurality of memory cells, and a memory controller configured to calculate a bit error rate when reading data from a block of the blocks and obtain an equation representing temporal changes in the bit error rate for the block, and based on the obtained equation, determine, for the block, a timing for performing a next refresh operation by which data that have been written to the block are rewritten.Type: GrantFiled: February 24, 2020Date of Patent: October 5, 2021Assignee: KIOXIA CORPORATIONInventor: Makoto Kuribara
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Publication number: 20210295937Abstract: According to one embodiment, a memory system includes a non-volatile memory and a controller. The memory includes a plurality of storage areas. Each of the storage areas includes a plurality of memory cells to which threshold voltages are set in accordance with data. The controller acquires a first threshold voltage distribution of memory cells in a first storage area of the storage areas. The controller acquires a second threshold voltage distribution of memory cells in a second storage area of the storage areas. The controller detects non-normalcy in the first storage area or the second storage area from a first divergence quantity between the first threshold voltage distribution and the second threshold voltage distribution.Type: ApplicationFiled: September 3, 2020Publication date: September 23, 2021Applicant: Kioxia CorporationInventors: Akiyoshi HASHIMOTO, Makoto KURIBARA, Takeshi TOMIZAWA, Katsuhiko UEKI
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Publication number: 20210089391Abstract: According to one embodiment, a memory system includes a non-volatile semiconductor memory having a plurality of blocks each including a plurality of memory cells, and a memory controller configured to calculate a bit error rate when reading data from a block of the blocks and obtain an equation representing temporal changes in the bit error rate for the block, and based on the obtained equation, determine, for the block, a timing for performing a next refresh operation by which data that have been written to the block are rewritten.Type: ApplicationFiled: February 24, 2020Publication date: March 25, 2021Inventor: Makoto KURIBARA
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Patent number: 10347353Abstract: According to one embodiment, a memory system includes a semiconductor memory and a memory controller. The memory controller writes a first data group in the semiconductor memory and then reads the first data group from the semiconductor memory. The memory controller counts a number of first data and a number of second data based on a comparison of a second data group with a third data group. The memory controller changes a first charge threshold based on the number of first data and the number of second data. The second data group is the first data group at the time of writing to the semiconductor memory. The third data group is the first data group read from the semiconductor memory. The first data is data changed from a first code to a second code. The second data is data changed from the second code to the first code.Type: GrantFiled: June 26, 2017Date of Patent: July 9, 2019Assignee: TOSHIBA MEMORY CORPORATIONInventors: Makoto Kuribara, Katsuhiko Ueki, Yoshihisa Kojima
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Publication number: 20170301402Abstract: According to one embodiment, a memory system includes a semiconductor memory and a memory controller. The memory controller writes a first data group in the semiconductor memory and then reads the first data group from the semiconductor memory. The memory controller counts a number of first data and a number of second data based on a comparison of a second data group with a third data group. The memory controller changes a first charge threshold based on the number of first data and the number of second data. The second data group is the first data group at the time of writing to the semiconductor memory. The third data group is the first data group read from the semiconductor memory. The first data is data changed from a first code to a second code. The second data is data changed from the second code to the first code.Type: ApplicationFiled: June 26, 2017Publication date: October 19, 2017Applicant: TOSHIBA MEMORY CORPORATIONInventors: Makoto KURIBARA, Katsuhiko UEKI, Yoshihisa KOJIMA
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Patent number: 9711240Abstract: According to one embodiment, a memory system includes a semiconductor memory and a memory controller. The memory controller writes a first data group in the semiconductor memory and then reads the first data group from the semiconductor memory. The memory controller counts a number of first data and a number of second data based on a comparison of a second data group with a third data group. The memory controller changes a first charge threshold based on the number of first data and the number of second data. The second data group is the first data group at the time of writing to the semiconductor memory. The third data group is the first data group read from the semiconductor memory. The first data is data changed from a first code to a second code. The second data is data changed from the second code to the first code.Type: GrantFiled: September 10, 2015Date of Patent: July 18, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Makoto Kuribara, Katsuhiko Ueki, Yoshihisa Kojima
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Publication number: 20160203873Abstract: According to one embodiment, a memory system includes a semiconductor memory and a memory controller. The memory controller writes a first data group in the semiconductor memory and then reads the first data group from the semiconductor memory. The memory controller counts a number of first data and a number of second data based on a comparison of a second data group with a third data group. The memory controller changes a first charge threshold based on the number of first data and the number of second data. The second data group is the first data group at the time of writing to the semiconductor memory. The third data group is the first data group read from the semiconductor memory. The first data is data changed from a first code to a second code. The second data is data changed from the second code to the first code.Type: ApplicationFiled: September 10, 2015Publication date: July 14, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Makoto Kuribara, Katsuhiko Ueki, Yoshihisa Kojima