Patents by Inventor Makoto Matsushima
Makoto Matsushima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11966458Abstract: An authentication method is used by an automated driving system that includes a vehicle and an external device, the external device communicating with the vehicle to cause the vehicle to implement automated driving. The vehicle holds a first certificate that certifies validity of the vehicle. The external device holds a second certificate that certifies validity of the external device. The authentication method includes: validating a third certificate that certifies validity of a combination of the vehicle and the external device, in accordance with a result of device authentication performed between the vehicle and the external device by reference to the first certificate and the second certificate.Type: GrantFiled: July 21, 2021Date of Patent: April 23, 2024Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICAInventors: Yoshihiro Ujiie, Hideki Matsushima, Makoto Fujiwara
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Patent number: 7953145Abstract: A PWM signal generating circuit outputs a stable PWM signal for increasing and decreasing a duty ratio at a predetermined rate within a predetermined period without requiring an improvement of a process capacity of a CPU as compared to a conventional PWM signal generating circuit. The PWM signal generating circuit consists of a plurality of circuit elements each of which outputs a digital signal. A first counter circuit periodically changes a PWM signal output therefrom into an active state. A second counter circuit changes the PWM signal, which has been changed into the active state by the first counter circuit, into an inactive state within each cycle. The second counter circuit increases and decreases an active-to-inactive time period from a time when the PWM signal is changed into the active state to a time when the PWM signal is changed into the inactive state.Type: GrantFiled: April 2, 2008Date of Patent: May 31, 2011Assignee: Ricoh Company, Ltd.Inventor: Makoto Matsushima
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Patent number: 7701187Abstract: A DC converter with a halt mode setting is disclosed for preventing the occurrence of over-current while alleviating the increase in the size of circuits, along with a method for setting up such a halt mode. The DC converter includes a semiconductor switch, a clock generator for outputting a clock signal to a gate of the semiconductor switch to be utilized for controlling an on/off time of the semiconductor switch such that a predetermined power is output from the generator, and a drive circuit for switching the semiconductor switch to the continuous-on state according to a halt mode setting requirement regardless of the clock signal, when the semiconductor switch, normally repeating on/off operations responsive to the clock signal, is in its off-state.Type: GrantFiled: July 1, 2008Date of Patent: April 20, 2010Assignee: Ricoh Company, Ltd.Inventors: Katsuhiko Manabe, Tomonari Katoh, Minoru Sugiyama, Makoto Matsushima, Tadayoshi Ueda
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Publication number: 20080272759Abstract: A DC converter with a halt mode setting is disclosed for preventing the occurrence of over-current while alleviating the increase in the size of circuits, along with a method for setting up such a halt mode. The DC converter includes a semiconductor switch, a clock generator for outputting a clock signal to a gate of the semiconductor switch to be utilized for controlling an on/off time of the semiconductor switch such that a predetermined power is output from the generator, and a drive circuit for switching the semiconductor switch to the continuous-on state according to a halt mode setting requirement regardless of the clock signal, when the semiconductor switch, normally repeating on/off operations responsive to the clock signal, is in its off-state.Type: ApplicationFiled: July 1, 2008Publication date: November 6, 2008Inventors: Katsuhiko Manabe, Tomonari Katoh, Minoru Sugiyama, Makoto Matsushima, Tadayoshi Ueda
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Publication number: 20080203933Abstract: A PWM signal generating circuit outputs a stable PWM signal for increasing and deceasing a duty ratio at a predetermined rate within a predetermined period without requiring an improvement of a process capacity of a CPU as compared to a conventional PWM signal generating circuit. The PWM signal generating circuit consists of a plurality of circuit elements each of which outputs a digital signal. A first counter circuit periodically changes a PWM signal output therefrom into an active state. A second counter circuit changes the PWM signal, which has been changed into the active state by the first counter circuit, into an inactive state within each cycle. The second counter circuit increases and decreases an active-to-inactive time period from a time when the PWM signal is changed into the active state to a time when the PWM signal is changed into the inactive state.Type: ApplicationFiled: April 2, 2008Publication date: August 28, 2008Applicant: Ricoh Company, Ltd.Inventor: Makoto Matsushima
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Publication number: 20080197872Abstract: A disclosed semiconductor chip includes a first connection pad adapted to input an input signal; and a second connection pad adapted to selectively output, according to a test mode signal input to the semiconductor chip, one of the input signal and an output signal from the semiconductor chip.Type: ApplicationFiled: January 15, 2008Publication date: August 21, 2008Inventor: Makoto Matsushima
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Patent number: 7408334Abstract: A DC converter with a halt mode setting is disclosed for preventing the occurrence of over-current while alleviating the increase in the size of circuits, along with a method for setting up such a halt mode. The DC converter includes a semiconductor switch, a clock generator for outputting a clock signal to a gate of the semiconductor switch to be utilized for controlling an on/off time of the semiconductor switch such that a predetermined power is output from the generator, and a drive circuit for switching the semiconductor switch to the continuous-on state according to a halt mode setting requirement regardless of the clock signal, when the semiconductor switch, normally repeating on/off operations responsive to the clock signal, is in its off-state.Type: GrantFiled: February 13, 2007Date of Patent: August 5, 2008Assignee: Ricoh Company, Ltd.Inventors: Katsuhiko Manabe, Tomonari Katoh, Minoru Sugiyama, Makoto Matsushima, Tadayoshi Ueda
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Patent number: 7372902Abstract: A PWM signal generating circuit outputs a stable PWM signal for increasing and deceasing a duty ratio at a predetermined rate within a predetermined period without requiring an improvement of a process capacity of a CPU as compared to a conventional PWM signal generating circuit. The PWM signal generating circuit consists of a plurality of circuit elements each of which outputs a digital signal. A first counter circuit periodically changes a PWM signal output therefrom into an active state. A second counter circuit changes the PWM signal, which has been changed into the active state by the first counter circuit, into an inactive state within each cycle. The second counter circuit increases and decreases an active-to-inactive time period from a time when the PWM signal is changed into the active state to a time when the PWM signal is changed into the inactive state.Type: GrantFiled: October 29, 2003Date of Patent: May 13, 2008Assignee: Ricoh Company, Ltd.Inventor: Makoto Matsushima
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Publication number: 20070145963Abstract: A DC converter with a halt mode setting is disclosed for preventing the occurrence of over-current while alleviating the increase in the size of circuits, along with a method for setting up such a halt mode. The DC converter includes a semiconductor switch, a clock generator for outputting a clock signal to a gate of the semiconductor switch to be utilized for controlling an on/off time of the semiconductor switch such that a predetermined power is output from the generator, and a drive circuit for switching the semiconductor switch to the continuous-on state according to a halt mode setting requirement regardless of the clock signal, when the semiconductor switch, normally repeating on/off operations responsive to the clock signal, is in its off-state.Type: ApplicationFiled: February 13, 2007Publication date: June 28, 2007Inventors: Katsuhiko Manabe, Tomonari Katoh, Minoru Sugiyama, Makoto Matsushima, Tadayoshi Ueda
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Patent number: 7193400Abstract: A DC converter with a halt mode setting is disclosed for preventing the occurrence of over-current while alleviating the increase in the size of circuits, along with a method for setting up such a halt mode. The DC converter includes a semiconductor switch, a clock generator for outputting a clock signal to a gate of the semiconductor switch to be utilized for controlling an on/off time of the semiconductor switch such that a predetermined power is output from the generator, and a drive circuit for switching the semiconductor switch to the continuous-on state according to a halt mode setting requirement regardless of the clock signal, when the semiconductor switch, normally repeating on/off operations responsive to the clock signal, is in its off-state.Type: GrantFiled: February 10, 2006Date of Patent: March 20, 2007Assignee: Ricoh Company, Ltd.Inventors: Katsuhiko Manabe, Tomonari Katoh, Minoru Sugiyama, Makoto Matsushima, Tadayoshi Ueda
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Patent number: 7146194Abstract: An amplifying circuit includes a battery power source, a regulator that regulates an output of the battery power source and generates a reference voltage, and a signal ground generating device that generates and outputs a signal ground by changing the reference voltage in accordance with deterioration detected from the battery power source. An operational amplifier is provided to amplify and output a signal having prescribed waveform to be input to a speaker. The operational amplifier uses a battery power source as a driving power source of its own. The signal ground is positioned at a center of vibration amplitude of the waveform.Type: GrantFiled: September 30, 2003Date of Patent: December 5, 2006Assignee: Ricoh Company, Ltd.Inventors: Makoto Matsushima, Katsuhiko Manabe
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Patent number: 7075279Abstract: A DC converter with a halt mode setting is disclosed for preventing the occurrence of over-current while alleviating the increase in the size of circuits, along with a method for setting up such a halt mode. The DC converter includes a semiconductor switch, a clock generator for outputting a clock signal to a gate of the semiconductor switch to be utilized for controlling an on/off time of the semiconductor switch such that a predetermined power is output from the generator, and a drive circuit for switching the semiconductor switch to the continuous-on state according to a halt mode setting requirement regardless of the clock signal, when the semiconductor switch, normally repeating on/off operations responsive to the clock signal, is in its off-state.Type: GrantFiled: June 30, 2005Date of Patent: July 11, 2006Assignee: Ricoh Company, Ltd.Inventors: Katsuhiko Manabe, Tomonari Katoh, Minoru Sugiyama, Makoto Matsushima, Tadayoshi Ueda
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Publication number: 20060125459Abstract: A DC converter with a halt mode setting is disclosed for preventing the occurrence of over-current while alleviating the increase in the size of circuits, along with a method for setting up such a halt mode. The DC converter includes a semiconductor switch, a clock generator for outputting a clock signal to a gate of the semiconductor switch to be utilized for controlling an on/off time of the semiconductor switch such that a predetermined power is output from the generator, and a drive circuit for switching the semiconductor switch to the continuous-on state according to a halt mode setting requirement regardless of the clock signal, when the semiconductor switch, normally repeating on/off operations responsive to the clock signal, is in its off-state.Type: ApplicationFiled: February 10, 2006Publication date: June 15, 2006Inventors: Katsuhiko Manabe, Tomonari Katoh, Minoru Sugiyama, Makoto Matsushima, Tadayoshi Ueda
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Publication number: 20060001411Abstract: A DC converter with a halt mode setting is disclosed for preventing the occurrence of over-current while alleviating the increase in the size of circuits, along with a method for setting up such a halt mode. The DC converter includes a semiconductor switch, a clock generator for outputting a clock signal to a gate of the semiconductor switch to be utilized for controlling an on/off time of the semiconductor switch such that a predetermined power is output from the generator, and a drive circuit for switching the semiconductor switch to the continuous-on state according to a halt mode setting requirement regardless of the clock signal, when the semiconductor switch, normally repeating on/off operations responsive to the clock signal, is in its off-state.Type: ApplicationFiled: June 30, 2005Publication date: January 5, 2006Inventors: Katsuhiko Manabe, Tomonari Katoh, Minoru Sugiyama, Makoto Matsushima, Tadayoshi Ueda
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Patent number: 6922043Abstract: A DC converter with a halt mode setting is disclosed for preventing the occurrence of over-current while alleviating the increase in the size of circuits, along with a method for setting up such a halt mode. The DC converter includes a semiconductor switch, a clock generator for outputting a clock signal to a gate of the semiconductor switch to be utilized for controlling an on/off time of the semiconductor switch such that a predetermined power is output from the generator, and a drive circuit for switching the semiconductor switch to the continuous-on state according to a halt mode setting requirement regardless of the clock signal, when the semiconductor switch, normally repeating on/off operations responsive to the clock signal, is in its off-state.Type: GrantFiled: September 3, 2003Date of Patent: July 26, 2005Assignee: Ricoh Company, LTDInventors: Katsuhiko Manabe, Tomonari Katoh, Minoru Sugiyama, Makoto Matsushima, Tadayoshi Ueda
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Publication number: 20040240540Abstract: A PWM signal generating circuit outputs a stable PWM signal for increasing and deceasing a duty ratio at a predetermined rate within a predetermined period without requiring an improvement of a process capacity of a CPU as compared to a conventional PWM signal generating circuit. The PWM signal generating circuit consists of a plurality of circuit elements each of which outputs a digital signal. A first counter circuit periodically changes a PWM signal output therefrom into an active state. A second counter circuit changes the PWM signal, which has been changed into the active state by the first counter circuit, into an inactive state within each cycle. The second counter circuit increases and decreases an active-to-inactive time period from a time when the PWM signal is changed into the active state to a time when the PWM signal is changed into the inactive state.Type: ApplicationFiled: October 29, 2003Publication date: December 2, 2004Inventor: Makoto Matsushima
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Publication number: 20040116162Abstract: An amplifying circuit includes a battery power source, a regulator that regulates an output of the battery power source and generates a reference voltage, and a signal ground generating device that generates and outputs a signal ground by changing the reference voltage in accordance with deterioration detected from the battery power source. An operational amplifier is provided to amplify and output a signal having prescribed waveform to be input to a speaker. The operational amplifier uses a battery power source as a driving power source of its own. The signal ground is positioned at a center of vibration amplitude of the waveform.Type: ApplicationFiled: September 30, 2003Publication date: June 17, 2004Inventors: Makoto Matsushima, Katsuhiko Manabe
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Publication number: 20040104715Abstract: A DC converter with a halt mode setting is disclosed for preventing the occurrence of over-current while alleviating the increase in the size of circuits, along with a method for setting up such a halt mode. The DC converter includes a semiconductor switch, a clock generator for outputting a clock signal to a gate of the semiconductor switch to be utilized for controlling an on/off time of the semiconductor switch such that a predetermined power is output from the generator, and a drive circuit for switching the semiconductor switch to the continuous-on state according to a halt mode setting requirement regardless of the clock signal, when the semiconductor switch, normally repeating on/off operations responsive to the clock signal, is in its off-state.Type: ApplicationFiled: September 3, 2003Publication date: June 3, 2004Inventors: Katsuhiko Manabe, Tomonari Katoh, Minoru Sugiyama, Makoto Matsushima, Tadayoshi Ueda
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Patent number: 5598160Abstract: A level-controlling unit consisting of an inverter controls a level of a given pulse signal, the level controlling being performed in a predetermined manner. An analog-signal producing unit consisting of a low-pass filter produces an analog signal by integrating the pulse signal having undergone the level controlling. An analog-signal processing unit consisting of A-D converter processes the analog signal with a dynamic range thereof so as to supply a digital signal, the dynamic range being defined by a predetermined reference level. The predetermined manner is such that a substantial possible level variation extent of the analog signal received by the analog-signal processing unit corresponds to the dynamic range.Type: GrantFiled: October 11, 1994Date of Patent: January 28, 1997Assignee: Ricoh Company, Ltd.Inventor: Makoto Matsushima
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Patent number: 5453788Abstract: An image processing apparatus includes: a first transforming device for transforming encoded data into discrete cosine transform coefficient data segmented into processing blocks, each block being formed of a matrix of m.times.n pixels; and a setting device for setting the values of M and N defining the size of a matrix forming each processing block used in inverse discrete cosine transform. The image processing apparatus also includes a data preparing circuit for adding discrete cosine transform coefficient data to, or deleting discrete cosine transform coefficient data from, a high-frequency domain of the discrete cosine transform coefficient data and segmented into processing blocks, each block being formed of a matrix of m.times.n pixels, and for preparing discrete cosine transform coefficient data segmented into processing blocks, each block being formed of a matrix of M.times.Type: GrantFiled: February 9, 1994Date of Patent: September 26, 1995Assignee: Ricoh Company, Ltd.Inventors: Makoto Matsushima, Ryo Fukui