Abstract: A memory device includes a plurality of memory cell transistors, a first word line, a controller, and a storage circuit. Each of the plurality of memory cell transistors stores a plurality of pieces of bit data. The first word line is connected to a plurality of first memory cell transistors in the plurality of memory cell transistors. The controller performs a loop process including repetition of a program loop including a program operation and a first verification operation. The storage circuit stores status information. The controller performs the loop process, then performs a second verification operation, and stores first status data corresponding to a result of the loop process and second status data corresponding to a result of the second verification operation in the storage circuit, in a write operation using the plurality of first memory cell transistors as targets.

Abstract: A memory device includes a plurality of memory cell transistors, a first word line, a controller, and a storage circuit. Each of the plurality of memory cell transistors stores a plurality of pieces of bit data. The first word line is connected to a plurality of first memory cell transistors in the plurality of memory cell transistors. The controller performs a loop process including repetition of a program loop including a program operation and a first verification operation. The storage circuit stores status information. The controller performs the loop process, then performs a second verification operation, and stores first status data corresponding to a result of the loop process and second status data corresponding to a result of the second verification operation in the storage circuit, in a write operation using the plurality of first memory cell transistors as targets.

Abstract: A semiconductor storage device has a memory cell array, a plurality of word lines, a plurality of bit lines, and a plurality of blocks including a group of at least some memory cells, a defect information storage block that stores defect information in the memory cell array, a first defect detection circuitry that reads data of at least some memory cells in the defect information storage block, verifies the data, and determines whether there is a defect in the defect information storage block, a second defect detection circuitry that changes a read voltage level for reading the data of the memory cells, rereads data of at least some memory cells in the defect information storage block, verifies the data, and determines whether there is the defect in the defect information storage block, and a defect determination circuitry that determines the defect information storage block as a defective block.

Abstract: A semiconductor storage device has a memory cell array, a plurality of word lines, a plurality of bit lines, and a plurality of blocks including a group of at least some memory cells, a defect information storage block that stores defect information in the memory cell array, a first defect detection circuitry that reads data of at least some memory cells in the defect information storage block, verifies the data, and determines whether there is a defect in the defect information storage block, a second defect detection circuitry that changes a read voltage level for reading the data of the memory cells, rereads data of at least some memory cells in the defect information storage block, verifies the data, and determines whether there is the defect in the defect information storage block, and a defect determination circuitry that determines the defect information storage block as a defective block.

Abstract: A semiconductor memory device, in which interference between adjoining cells can be reduced and an expansion of a chip area can be suppressed, comprising: a memory cell array in which plural memory cells connected to plural word lines and plural bit lines are disposed in a matrix form; sense amplifiers each of which is to be connected to each of the bit lines; a control circuit which controls voltages of the word lines and the bit lines, and programs data into the memory cells or reads data from the memory cells; wherein the plural bit lines include at least a first, a second, a third and a fourth bit lines adjoining to each other, and the sense amplifiers include at least a first and a second sense amplifiers, a first and a fourth selection transistors which are provided between the first and the fourth bit lines and the first sense amplifier, and connect the first and the fourth bit lines to the first sense amplifier; and a second and a third selection transistors which are provided between the second and t

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array and a control circuit. The memory cell array is composed of a plurality of memory cells arranged in a matrix pattern. The control circuit sets a first flag data in a second memory cell in order to write data to a plurality of first memory cells of memory cell array, the second memory cell having been selected at the same time as the first memory cells, determines whether the first flag data is set in the second memory cell before data is read from the first memory cells, and reads no data from the first memory cells and outputs data of first logic level if the first flag data is not set in the second memory cell, and reads data from the first memory cells if the first flag data is set in the second memory cell.

Abstract: A semiconductor memory device, in which interference between adjoining cells can be reduced and an expansion of a chip area can be suppressed, comprising: a memory cell array in which plural memory cells connected to plural word lines and plural bit lines are disposed in a matrix form; sense amplifiers each of which is to be connected to each of the bit lines; a control circuit which controls voltages of the word lines and the bit lines, and programs data into the memory cells or reads data from the memory cells; wherein the plural bit lines include at least a first, a second, a third and a fourth bit lines adjoining to each other, and the sense amplifiers include at least a first and a second sense amplifiers, a first and a fourth selection transistors which are provided between the first and the fourth bit lines and the first sense amplifier, and connect the first and the fourth bit lines to the first sense amplifier; and a second and a third selection transistors which are provided between the second and t