Abstract: An optical modulator includes a substrate having a main surface including a first area and a second area, an optical modulation portion disposed on the first area, and an optical waveguide portion disposed on the second area. The optical modulation portion includes a first mesa waveguide and an electrode connected to the first mesa waveguide. The first mesa waveguide includes a p-type semiconductor layer, a first core layer, and an n-type semiconductor layer. The optical waveguide portion includes a second mesa waveguide. The second mesa waveguide includes a first cladding layer, a second core layer, and a second cladding layer. The second core layer is optically coupled to the first core layer. The first cladding layer contains a p-type dopant and protons. The second cladding layer contains an n-type dopant.

Abstract: An optical modulator includes a substrate having a main surface including a first area and a second area, an optical modulation portion disposed on the first area, and an optical waveguide portion disposed on the second area. The optical modulation portion includes a first mesa waveguide and an electrode connected to the first mesa waveguide. The first mesa waveguide includes a p-type semiconductor layer, a first core layer, and an n-type semiconductor layer. The optical waveguide portion includes a second mesa waveguide. The second mesa waveguide includes a first cladding layer, a second core layer, and a second cladding layer. The second core layer is optically coupled to the first core layer. The first cladding layer contains a p-type dopant and protons. The second cladding layer contains an n-type dopant.

Abstract: According to one embodiment, an automatic analyzing apparatus includes a liquid tank, a first pump, a dispensing probe, and a thermal exchanger. The liquid tank stores a first liquid. The first pump pressurizes and sends the first liquid supplied from the liquid tank. The dispensing probe uses the first liquid that is sent out from the first pump as a pressure transmitting medium. The thermal exchanger exchanges heat between an atmosphere in the automatic analyzing apparatus and the first liquid in at least a part of a first flow path connecting the first pump to the liquid tank.

Abstract: To provide a semiconductor device having improved reliability. An element isolation region comprised mainly of silicon oxide is buried in a trench formed in a semiconductor substrate. The semiconductor substrate in an active region surrounded by the element isolation region has thereon a gate electrode for MISFET via a gate insulating film. The gate electrode partially extends over the element isolation region and the trench has a nitrided inner surface. Below the gate electrode, fluorine is introduced into the vicinity of a boundary between the element isolation region and a channel region of MISFET.

Abstract: To predict a temperature rise amount due to self-heating of a resistance value of a gate electrode with high accuracy in an HCI accelerated stress test. A gate electrode for gate resistance measurement (for temperature monitoring) that has contacts on its both sides, respectively, is disposed adjacent to the gate electrode. At the time of gate ON of the gate electrode, voltages that are substantially the same voltages as that of the gate electrode and have a minute potential difference between its contacts are applied between the contacts of the gate electrode for gate resistance measurement (for temperature monitoring), and a resistance value of the gate electrode for gate resistance measurement (for temperature monitoring) is measured.

Abstract: To provide a semiconductor device having improved reliability. An element isolation region comprised mainly of silicon oxide is buried in a trench formed in a semiconductor substrate. The semiconductor substrate in an active region. surrounded by the element isolation region has thereon a gate electrode for MISFET via a gate insulating film. The gate electrode partially extends over the element isolation legion and the trench has a nitrided inner surface. Below the gate electrode, fluorine is introduced into the vicinity of a boundary between the element isolation region and a channel region of MISFET.

Abstract: In a semiconductor device, an abnormality monitor unit detects whether abnormal leakage current has been generated from a first functional module or a second functional module on the basis of a comparison between a change in voltage at a first node between the first functional module and a first power switch when the first power switch is in an off state and a change in voltage at a second node between the second functional module and a second power switch when the second power switch is in the off state.

Abstract: According to one embodiment, an automatic analyzing apparatus includes a liquid tank, a first pump, a dispensing probe, and a thermal exchanger. The liquid tank stores a first liquid. The first pump pressurizes and sends the first liquid supplied from the liquid tank. The dispensing probe uses the first liquid that is sent out from the first pump as a pressure transmitting medium. The thermal exchanger exchanges heat between an atmosphere in the automatic analyzing apparatus and the first liquid in at least a part of a first flow path connecting the first pump to the liquid tank.

Abstract: To predict a temperature rise amount due to self-heating of a resistance value of a gate electrode with high accuracy in an HCI accelerated stress test. A gate electrode for gate resistance measurement (for temperature monitoring) that has contacts on its both sides, respectively, is disposed adjacent to the gate electrode. At the time of gate ON of the gate electrode, voltages that are substantially the same voltages as that of the gate electrode and have a minute potential difference between its contacts are applied between the contacts of the gate electrode for gate resistance measurement (for temperature monitoring), and a resistance value of the gate electrode for gate resistance measurement (for temperature monitoring) is measured.

Abstract: In a semiconductor device, an abnormality monitor unit detects whether abnormal leakage current has been generated from a first functional module or a second functional module on the basis of a comparison between a change in voltage at a first node between the first functional module and a first power switch when the first power switch is in an off state and a change in voltage at a second node between the second functional module and a second power switch when the second power switch is in the off state.

Abstract: To provide a semiconductor device having improved reliability. An element isolation region comprised mainly of silicon oxide is buried in a trench formed in a semiconductor substrate. The semiconductor substrate in an active region surrounded by the element isolation region has thereon a gate electrode for MISFET via a gate insulating film. The gate electrode partially extends over the element isolation region and the trench has a nitrided inner surface. Below the gate electrode, fluorine is introduced into the vicinity of a boundary between the element isolation region and a channel region of MISFET.

Abstract: To prevent dew condensation in a crankcase in a lower part of the crankcase, wherein an oil pan is an integral part of an internal combustion engine, to prevent lubricating oil from being diluted. A crankcase cover covers at least an oil pan out of a crankcase and is provided to the bottom of the crankcase. A heat insulating material is provided between the crankcase and the crankcase cover. A cooling fluid passage for providing a circulation to cool a cylinder or a cylinder head is provided between the crankcase and the crankcase cover. A passage at least one end of which reaches a cylinder head from a crankcase via a cylinder block forms at least a part of a blowby gas passage, is directly provided to the crankcase, the cylinder block and the cylinder head. A flow control valve is arranged in the cylinder block or the cylinder head.

Abstract: To prevent dew condensation in a crankcase in a lower part of the crankcase, wherein an oil pan is an integral part of an internal combustion engine, to prevent lubricating oil from being diluted. A crankcase cover covers at least an oil pan out of a crankcase and is provided to the bottom of the crankcase. A heat insulating material is provided between the crankcase and the crankcase cover. A cooling fluid passage for providing a circulation to cool a cylinder or a cylinder head is provided between the crankcase and the crankcase cover. A passage at least one end of which reaches a cylinder head from a crankcase via a cylinder block forms at least a part of a blowby gas passage, is directly provided to the crankcase, the cylinder block and the cylinder head. A flow control valve is arranged in the cylinder block or the cylinder head.

Abstract: A technique for a semiconductor device is provided that includes forming circuit regions on a device formation region and device isolation regions on a semiconductor substrate, a ratio of the width of a device isolation region to the width of adjacent circuit regions thereto is set at 2 to 50. A design method is also provided and includes conducting measurements such as of thicknesses of a pad oxide film and a nitride film, the internal stress of the nitride film, the width of both device formation and isolation regions, the depth of the etched portion of the nitride film for forming the groove in a device isolation region, conducting stress analysis in the proximity of the groove due to thermal oxidation, and setting values pertaining to the width of the device formation region and of the device isolation region which do not lead to occurrence of dislocation.

Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel s

Abstract: A technique for a semiconductor device is provided that includes forming circuit regions on a device formation region and device isolation regions on a semiconductor substrate, a ratio of the width of a device isolation region to the width of adjacent circuit regions thereto is set at 2 to 50. A design method is also provided and includes conducting measurements such as of thicknesses of a pad oxide film and a nitride film, the internal stress of the nitride film, the width of both device formation and isolation regions, the depth of the etched portion of the nitride film for forming the groove in a device isolation region, conducting stress analysis in the proximity of the groove due to thermal oxidation, and setting values pertaining to the width of the device formation region and of the device isolation region which do not lead to occurrence of dislocation.

Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel s

Abstract: A method is provided of fabricating a semiconductor device that includes forming a silicon oxide film on a semiconductor substrate. A silicon nitrite film may be formed on the silicon oxide film. A portion of the silicon nitrite film and the silicon oxide film may be removed at a desired portion. Additionally, a groove may be formed in the semiconductor substrate in the portion in which the silicon oxide film is removed. A part of the silicon oxide film may be etched back around the groove with hydrofluoric acid type at the portion in which the silicon nitrite film is located above. Additionally, an oxidized film may be formed in the groove of the semiconductor substrate and the groove may be oxidized.

Abstract: A field oxide film 3 in a region where relief cells are formed is made wider than the field oxide film 3 in a region where normal memory cells are formed thereby to make a field relaxation layer 8r of the relief cells deeper than the field relaxation layer 8 of the normal cells, and the depletion layer of the sources and drains (n-type semiconductor regions) of the relief cells is widened to weaken the junction field.

Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel s