Patents by Inventor Makoto Ohtani

Makoto Ohtani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11955919
    Abstract: An electric motor system includes a battery, an inverter, an electric motor, a zero-phase switching arm and a control unit. The inverter converts DC power output from the battery into three-phase AC power and outputs the three-phase AC power to the electric motor. A rotor of the electric motor rotates by the three-phase AC power output from the inverter. A neural point of the electric motor is connected to the zero-phase switching arm. A zero-phase current flowing through respective windings of the electric motor is adjusted by switching of the zero-phase switching arm. By this means, in the electric motor system, torque is generated at the rotor also using the zero-phase current as well as a three-phase AC current flowing through the respective windings.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: April 9, 2024
    Assignee: DENSO CORPORATION
    Inventors: Makoto Taniguchi, Kazunari Moriya, Kenji Hiramoto, Hideo Nakai, Yuuko Ohtani, Shinya Urata, Masafumi Namba
  • Patent number: 7923729
    Abstract: An active matrix substrate with a high aperture ratio is provided, which is capable of preventing electrical short circuits between pixel electrodes and auxiliary capacitive electrodes. Gate lines and auxiliary capacitive electrodes are formed on an insulated substrate. The auxiliary capacitive electrodes have holes formed therethrough. To cover the gate lines and the auxiliary capacitive electrodes, a first interlayer insulating film is formed, on which source lines, a semiconductor layer, and drain electrodes are formed. Then, a second interlayer insulating film is formed to cover all those layers. In the second interlayer insulating film, contact holes are formed to reach the drain electrodes in areas corresponding to the areas of the holes. Pixel electrodes formed on the second interlayer insulating film are connected to the drain electrodes through the contact holes.
    Type: Grant
    Filed: May 22, 2009
    Date of Patent: April 12, 2011
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kyoko Sawamizu, Makoto Ohtani, Yasushi Matsui
  • Publication number: 20090230399
    Abstract: An active matrix substrate with a high aperture ratio is provided, which is capable of preventing electrical short circuits between pixel electrodes and auxiliary capacitive electrodes. Gate lines and auxiliary capacitive electrodes are formed on an insulated substrate. The auxiliary capacitive electrodes have holes formed therethrough. To cover the gate lines and the auxiliary capacitive electrodes, a first interlayer insulating film is formed, on which source lines, a semiconductor layer, and drain electrodes are formed. Then, a second interlayer insulating film is formed to cover all those layers. In the second interlayer insulating film, contact holes are formed to reach the drain electrodes in areas corresponding to the areas of the holes. Pixel electrodes formed on the second interlayer insulating film are connected to the drain electrodes through the contact holes.
    Type: Application
    Filed: May 22, 2009
    Publication date: September 17, 2009
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Kyoko SAWAMIZU, Makoto OHTANI, Yasushi MATSUI
  • Patent number: 7554119
    Abstract: An active matrix substrate with a high aperture ratio is provided, which is capable of preventing electrical short circuits between pixel electrodes and auxiliary capacitive electrodes. Gate lines and auxiliary capacitive electrodes are formed on an insulated substrate. The auxiliary capacitive electrodes have holes formed therethrough. To cover the gate lines and the auxiliary capacitive electrodes, a first interlayer insulating film is formed, on which source lines, a semiconductor layer, and drain electrodes are formed. Then, a second interlayer insulating film is formed to cover all those layers. In the second interlayer insulating film, contact holes are formed to reach the drain electrodes in areas corresponding to the areas of the holes.
    Type: Grant
    Filed: November 16, 2005
    Date of Patent: June 30, 2009
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kyoko Sawamizu, Makoto Ohtani, Yasushi Matsui
  • Publication number: 20080118769
    Abstract: There is provided a method of manufacturing a thin film, in which not only high crystallinity and surface flatness can be realized but also dopant doping can be performed at high concentration. The method includes a low temperature highly doped layer growing step of performing dopant doping while growing the thin film at a given first temperature; an annealing step of interrupting the growth of the thin film and annealing the thin film at a given second temperature higher than the first temperature; and a high temperature lowly doped layer growing step of growing the thin film at the second temperature.
    Type: Application
    Filed: September 10, 2004
    Publication date: May 22, 2008
    Applicant: TOHOKU UNIVERSITY
    Inventors: Masashi Kawasaki, Akira Ohtomo, Tomoaki Fukumura, Atsushi Tsukazaki, Makoto Ohtani
  • Publication number: 20060169983
    Abstract: An active matrix substrate with a high aperture ratio is provided, which is capable of preventing electrical short circuits between pixel electrodes and auxiliary capacitive electrodes. Gate lines and auxiliary capacitive electrodes are formed on an insulated substrate. The auxiliary capacitive electrodes have holes formed therethrough. To cover the gate lines and the auxiliary capacitive electrodes, a first interlayer insulating film is formed, on which source lines, a semiconductor layer, and drain electrodes are formed. Then, a second interlayer insulating film is formed to cover all those layers. In the second interlayer insulating film, contact holes are formed to reach the drain electrodes in areas corresponding to the areas of the holes. Pixel electrodes formed on the second interlayer insulating film are connected to the drain electrodes through the contact holes.
    Type: Application
    Filed: November 16, 2005
    Publication date: August 3, 2006
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kyoko Sawamizu, Makoto Ohtani, Yasushi Matsui
  • Patent number: 5685944
    Abstract: A film transfer apparatus includes an apparatus casing having a feed-core support shaft for detachably mounting a feed core and a take-up core support shaft for detachably mounting a take-up core. The support shafts respectively include a transmission member for causing the feed core to provide a film ribbon take-up speed higher than a ribbon feed speed of the feed core. For slippably coupling the feed core rotation and the take-up core rotation, a slip coupling mechanism is provided. This mechanism is constituted by an engaged portion of the take-up core for engagement with a mating engaging portion of the take-up core support shaft. The engaged portion is elastically deformable to a non-transmission condition with application thereto of a force exceeding a predetermined level. Further, the engaged portion is provided with a mechanical strength smaller than the engaging portion.
    Type: Grant
    Filed: April 26, 1995
    Date of Patent: November 11, 1997
    Assignee: Fujicopian Co., Ltd.
    Inventors: Masahisa Nose, Hiroshi Kozaki, Kazuhiro Tanaka, Masahiko Ono, Kazuya Watanabe, Makoto Ohtani, Keiichiro Minegishi
  • Patent number: 5270845
    Abstract: An improved method for manufacturing a liquid crystal display unit substantially free from gate electrode breakage but with no increase in the number of manufacturing steps over the conventional method. The liquid crystal display unit includes a TFT array substrate including a plurality of gate electrode lines juxtaposed on a transparent insulating substrate, a plurality of source electrode lines arranged across the gate electrode lines, nonlinear active elements disposed at the intersections of the electrode lines, a confronting electrode substrate having a transparent conductive film on the surface thereof confronting the TFT array substrate, and a liquid crystal display material being held between the confronting electrode substrate and the TFT array substrate. Each of the gate electrode lines is constructed in the form of two layers. One of the two layers is made of display electrode material simultaneously with the formation of the display electrode.
    Type: Grant
    Filed: December 18, 1989
    Date of Patent: December 14, 1993
    Assignee: Mitsubishi Denki K.K.
    Inventors: Hirokazu Sakamoto, Masayuki Yokomizo, Masahiro Hayama, Takao Matsumoto, Naoki Nakagawa, Makoto Ohtani
  • Patent number: 5066106
    Abstract: A liquid crystal display device includes a transparent conductive film display electrode on a transparent insulating substrate, a plurality of lower layer source conductors disposed simultaneously with a plurality of gate electrode conductors on the substrate, the source conductors intersecting the gate electrode conductors, a gate insulation film on the gate electrode conductors, the lower layer source conductors, and the display electrode, a semiconductor film disposed on the gate insulation film at a position overlying the gate electrode conductors, a drain electrode connected to the display electrode and disposed on the semiconductor film and the gate insulation film, and an upper layer source electrode conductor connected to the lower layer source conductors, the upper layer source electrode conductor disposed on the gate insulation film and the semiconductor film and forming a double-layer structure with the lower layer source conductors.
    Type: Grant
    Filed: January 13, 1989
    Date of Patent: November 19, 1991
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hirokazu Sakamoto, Makoto Ohtani, Naoki Nakagawa, Taro Maejima, Masahiro Hayama