Abstract: A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogenide material and a memory cell constituted of a diode are stacked, and an initialization condition and a rewriting condition are changed in accordance with the layer where a selected memory cell is located. A current mirror circuit is selected in accordance with an operation, and at the same time, the initialization condition and the rewriting condition (here, reset condition) are changed in accordance with the operation by a control mechanism of the reset current in a voltage selection circuit and a current mirror circuit.

Abstract: Traffic between logic LSIs and memory is increasing year by year and there is demand for increase of capacity of communication between them and reduction of power consumption in the communication. Communication distances between LSIs can be reduced by stacking the LSIs. However, in a simple stack of logic LSIs and memory LSIs, it is difficult to ensure heat dissipation to cope with increasing heat densities and ensure transmission characteristics for fast communication with the outside of the stacked package. Also required is a connection topology that improves the performance of communication among the stacked LSIs while ensuring the versatility of the LSIs. An external-communication LSI, a memory LSI, and a logic LSI are stacked in this order in a semiconductor package and are interconnected by through silicon vias.

Abstract: In a test method of stacked LSIs connected by Through Silicon Vias, it is difficult to perform a failure diagnosis by using a conventional device test method to only one side of a silicon wafer, there is a possibility of yield degradation at a stacking time of LSIs, and a plurality of LSIs is connected to one Through Silicon Via so that it is necessary to select and remedy a defective Through Silicon Via taking into account all the device states. These problems cannot be solved by conventional test methods.

Abstract: A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogcnidc material and a memory cell constituted of a diode are stacked, and an initialization condition and a rewriting condition are changed in accordance with the layer where a selected memory cell is located. A current mirror circuit is selected in accordance with an operation, and at the same time, the initialization condition and the rewriting condition (here, reset condition) are changed in accordance with the operation by a control mechanism of the reset current in a voltage selection circuit and a current mirror circuit.

Abstract: A semiconductor device including a pair of stacked semiconductor ICs capable of communicating with each other by wireless. Each IC has: a transmitter circuit operable to send, by wireless, transmit data together with a clock signal deciding a transmission timing, and arranged so that the wireless transmission timing is adjustable; a receiver circuit operable to receive data in synchronization with a clock signal received by wireless, and arranged so that its wireless reception timing is adjustable; and a control circuit operable to perform timing adjustments of the transmitter and receiver circuits based on a result of authentication of data returned by the other IC in response to data transmitted through the transmitter circuit, and received by the receiver circuit. This arrangement for near field communication between stacked semiconductor ICs enables: reduction of the scale of a circuit for communication timing adjustment; and highly accurate adjustment of the communication timing.

Abstract: The performance of a whole system is improved by synchronizing communication and computations between stacked computing LSIs. Each of stacked an external communication LSI and a computing LSI has a PLL which multiplies a crystal oscillator clock signal, a clock pulse generator which distributes the clock signal, and flip-flop circuits. The computing LSI has a DLL circuit composed of a clock phase comparator, a delay controller, and a delay chain. In order to synchronize the communication and computations of the external communication LSI and the computing LSI, a synchronization reference clock signal is transmitted from the external communication LSI to the computing LSI via a through-electrode. An internal clock signal of the computing LSI is synchronized with the synchronization reference clock signal from the external communication LSI by the DLL circuit.

Abstract: A semiconductor device where multiple chips of identical design can be stacked, and the spacer and interposer eliminated, to improve three-dimensional coupling information transmission capability. A first semiconductor circuit including a three-dimensional coupling circuit (three-dimensional coupling transmission terminal group and three-dimensional coupling receiver terminal group); and a second semiconductor integrated circuit including a three-dimensional coupling circuit and feed-through electrode (power supply via hole and ground via hole); and a third semiconductor integrated circuit including a three-dimensional coupling circuit and feed-through electrode are stacked on the package substrate.

Abstract: In a semiconductor device in which a plurality of memory LSIs and a plurality of processor LSIs are stacked, as the number of stacked layers increase, the communication distance of data between a memory LSI and a processor LSI will increase. Therefore, the parasitic capacitance and parasitic resistance of the wiring used for the communication increase and, as a result of which, the power and speed performance of the entire system will be degraded. At least two or more of the combinations of a processor LSI 100 and a memory LSI 200 are stacked and the processor LSI 100 and the memory LSI 200 in the same combination are stacked adjacent to each other in the vertical direction.

Abstract: A semiconductor integrated circuit device which consumes less power and enables real-time processing. The semiconductor integrated circuit device includes thermal sensors which detect temperature and determine whether the detection result exceeds reference values and output the result, and a control block capable of controlling the operations of arithmetic blocks based on the output signals of the thermal sensors. The control block returns to an operation state from a suspended state with an interrupt signal based on the output signals of the thermal sensors and determines the operation conditions of the arithmetic blocks to ensure that the temperature conditions of the arithmetic blocks are satisfied. Thereby, power consumption is reduced and real-time processing efficiency is improved.

Abstract: In a semiconductor device in which a plurality of memory LSIs and a plurality of processor LSIs are stacked, as the number of stacked layers increase, the communication distance of data between a memory LSI and a processor LSI will increase. Therefore, the parasitic capacitance and parasitic resistance of the wiring used for the communication increase and, as a result of which, the power and speed performance of the entire system will be degraded. At least two or more of the combinations of a processor LSI 100 and a memory LSI 200 are stacked and the processor LSI 100 and the memory LSI 200 in the same combination are stacked adjacent to each other in the vertical direction.

Abstract: A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogenide material and a memory cell constituted of a diode are stacked, and an initialization condition and a rewriting condition are changed in accordance with the layer where a selected memory cell is located. A current mirror circuit is selected in accordance with an operation, and at the same time, the initialization condition and the rewriting condition (here, reset condition) are changed in accordance with the operation by a control mechanism of the reset current in a voltage selection circuit and a current mirror circuit.

Abstract: An interconnect configuration technology of making an access from an IP mounted on a semiconductor chip to an IP mounted on another semiconductor chip by transmitting and receiving a packet transferred through an interconnect built in a semiconductor chip among the chips using the 3D coupling technology. The device according to the technology has an initiator for transmitting an access request, a target for receiving the access request and transmitting an access response, a router for relaying the access request and the access response, and a 3D coupling circuit (three-dimensional transceiver) for performing communication with the outside, wherein the 3D coupling circuit is disposed adjacent to the router.

Abstract: In a semiconductor device in which a plurality of memory LSIs and a plurality of processor LSIs are stacked, as the number of stacked layers increase, the communication distance of data between a memory LSI and a processor LSI will increase. Therefore, the parasitic capacitance and parasitic resistance of the wiring used for the communication increase and, as a result of which, the power and speed performance of the entire system will be degraded. At least two or more of the combinations of a processor LSI 100 and a memory LSI 200 are stacked and the processor LSI 100 and the memory LSI 200 in the same combination are stacked adjacent to each other in the vertical direction.

Abstract: In a through-via-hole path of semiconductor chips stacked in N stages, repeater circuits are provided in the respective semiconductor chips. For example, a signal transmitted from an output buffer circuit of the semiconductor chip is transmitted to an input buffer circuit of the semiconductor chip via the repeater circuits of the respective semiconductor chips. The respective repeater circuits can isolate impedances on input sides and output sides, and therefore, a deterioration of a waveform quality accompanied by a parasitic capacitance parasitic on the through-via-hole path of the respective semiconductor chips can be reduced and a high speed signal can be transmitted.

Abstract: The performance of a whole system is improved by synchronizing communication and computations between stacked computing LSIs. Each of stacked an external communication LSI and a computing LSI has a PLL which multiplies a crystal oscillator clock signal, a clock pulse generator which distributes the clock signal, and flip-flop circuits. The computing LSI has a DLL circuit composed of a clock phase comparator, a delay controller, and a delay chain. In order to synchronize the communication and computations of the external communication LSI and the computing LSI, a synchronization reference clock signal is transmitted from the external communication LSI to the computing LSI via a through-electrode. An internal clock signal of the computing LSI is synchronized with the synchronization reference clock signal from the external communication LSI by the DLL circuit.

Abstract: The need for mediation operation is eliminated by adoption of a connection topology in which a circuit for executing one transmission (TR—00T), and a circuit for executing a plurality of receptions (TR—10R, TR—20R, TR—30R) are connected to one penetration-electrode group (for example, TSVGL—0). In order to implement the connection topology even in the case of piling up a plurality of LSIs one after another, in particular, a programmable memory element for designating respective penetration-electrode ports for use in transmit, or for us in receive, and address allocation of the respective penetration-electrode ports is mounted in stacked LSIs.

Abstract: The present invention is directed to facilitate debugging in a semiconductor integrated circuit device including a plurality of microprocessors. A semiconductor integrated circuit device includes: a plurality of processors; a plurality of debug interfaces enabling debugging of the corresponding processors; a plurality of common terminals shared by the plurality of debug interfaces; a selection circuit capable of selectively connecting the plurality of debug interfaces to the common terminals; and a controller capable of controlling selecting operation in the selection circuit in accordance with a predetermined instruction. A first selector capable of selectively connecting the plurality of debug interfaces to a TRST terminal in the terminal group conformed with the JTAG specifications, and a second selector capable of selectively connecting the plurality of debug interfaces to terminals other than the TRST terminal are provided.

Abstract: There is a need to ensure operation performance of a circuit region under DVFS control at low costs and highly precisely while a power-supply voltage change is made to the region. A first circuit (FVA) uses a first power-supply voltage (VDDA) for operation. A second circuit (NFVA) uses a second power-supply voltage (VDDB) for operation. A clock delay may be adjusted between paths for transmitting a clock to these circuits. When VDDA equals VDDB, a clock is distributed to FVA through a path that does not contain a delay device for phase adjustment. When the power-supply voltage for the FVA region is reduced, a clock is distributed to the FVA region based on a phase equivalent to one or two cycles of the clock displaced. Synchronization control is provided to synchronize clocks (CKAF and CKBF) and ensures operation so that a phase of two clocks to be compared fits in a range of design values while the power-supply voltage for the first circuit is changed.

Abstract: A semiconductor integrated circuit device capable of achieving improvement of I/O processing performance, reduction of power consumption, and reduction of cost is provided. Provided is a semiconductor integrated circuit device including, for example, a plurality of semiconductor chips stacked and mounted, the chips having data transceiving terminals bus-connected via through-vias, and data transmission and reception are performed via the bus with using the lowest source voltage among source voltages of internal core circuits of the chips. In accordance with that, a source voltage terminal of an n-th chip to be at the lowest source voltage is connected with source voltage terminals for data transceiving circuits of the other semiconductor chips via through-vias.

Abstract: As the transfer between a processor LSI and a memory has been increasing year by year, there is a demand for increasing the traffic amount and reducing the power required for communication. With this being the condition, a method of stacking LSIs thereby reducing the communication distance is being contemplated. However, the inventors have found that the reduction of cost in the stacking process and the increase in the degree of freedom of selecting the memory LSI to be stacked are required for a simple stacking of processor LSIs and memory LSIs as so far practiced. An external communication LSI including a circuit for performing the communication with the outside of the stacked LSI at a high rate of more than 1 GHz; a processor LSI including a general purpose CPU etc.; and a memory LSI including a DRAM etc. are stacked in this order and those LSIs are connected with one another with a through silicon via to enable a high speed and high volume communication at a shortest path.