Patents by Inventor Makoto SHIROSHITA

Makoto SHIROSHITA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230088233
    Abstract: A wiring board according to the present disclosure includes a core insulating layer, a first laminated body located on an upper surface of the core insulating layer, and a second laminated body located on a lower surface of the core insulating layer. Each of the first laminated body and the second laminated body has a structure in which at least four electrical conductor layers and at least three build-up insulating layers are alternately located. The electrical conductor layers include two types, that are a first electrical conductor layer and a second electrical conductor layer. In the electrical conductor layers in the first laminated body, at least a first outermost layer and a first innermost layer are the first electrical conductor layers, and a first intermediate layer located farther from the core insulating layer than the first innermost layer includes at least two or more of the second electrical conductor layers.
    Type: Application
    Filed: December 8, 2020
    Publication date: March 23, 2023
    Applicant: KYOCERA Corporation
    Inventors: Aki KAWASE, Makoto SHIROSHITA
  • Publication number: 20180151517
    Abstract: A semiconductor element mounting board includes: a circuit conductor disposed on the insulating board, a plurality of semiconductor element connection pads connected to the circuit conductor, a semiconductor element mounted on a surface of the insulating board, a first capacitor and a second capacitor disposed on a surface or an inside of the insulating board, and a first conductor path configured to connect the first capacitor between the semiconductor element connection pads, and a second conductor path configured to connect the second capacitor between the semiconductor element connection pads; and an inductance of the first conductor path is smaller than an inductance of the second conductor path, and capacitance of the first capacitor is smaller than capacitance of the second capacitor, and an internal inductance of the first capacitor is smaller than an internal inductance of the second capacitor.
    Type: Application
    Filed: November 29, 2016
    Publication date: May 31, 2018
    Applicant: KYOCERA Corporation
    Inventors: Makoto SHIROSHITA, Hisayoshi WADA
  • Patent number: 9984984
    Abstract: A semiconductor element mounting board includes: a circuit conductor disposed on the insulating board, a plurality of semiconductor element connection pads connected to the circuit conductor, a semiconductor element mounted on a surface of the insulating board, a first capacitor and a second capacitor disposed on a surface or an inside of the insulating board, and a first conductor path configured to connect the first capacitor between the semiconductor element connection pads, and a second conductor path configured to connect the second capacitor between the semiconductor element connection pads; and an inductance of the first conductor path is smaller than an inductance of the second conductor path, and capacitance of the first capacitor is smaller than capacitance of the second capacitor, and an internal inductance of the first capacitor is smaller than an internal inductance of the second capacitor.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: May 29, 2018
    Assignee: KYOCERA CORPORATION
    Inventors: Makoto Shiroshita, Hisayoshi Wada
  • Publication number: 20160380329
    Abstract: A waveguide structure of the present disclosure includes a first conductor layer, a plurality of dielectric strips which are formed so as to extend adjacently to one another on the upper surface of the first conductor layer, and a second conductor layer formed on the upper surface of the first conductor layer so as to cover the upper and side surfaces of the dielectric strips.
    Type: Application
    Filed: June 22, 2016
    Publication date: December 29, 2016
    Applicant: KYOCERA Corporation
    Inventors: Makoto SHIROSHITA, Kazuki HAYATA
  • Patent number: 9295154
    Abstract: A wiring board according to the present invention is provided with an insulating board and a connection pad, wherein the connection pad includes a main conductor layer formed of a low resistance material, a thin film resistor layer formed of a high resistance material and having a low soldering wettability, and a covering layer having a high soldering wettability, the main conductor layer, the thin film resistor layer, and the covering layer being sequentially laminated at the surface of the insulating layer in such a manner as to be electrically connected in series to each other, and the thin film resistor layer covers a main surface and a side surface of the main conductor layer, and further, a side surface of the thin film resistor layer is exposed from the covering layer.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: March 22, 2016
    Assignee: KYOCERA CIRCUIT SOLUTIONS, INC.
    Inventor: Makoto Shiroshita
  • Publication number: 20150305155
    Abstract: The wiring board according to the embodiment of the present invention includes a core substrate including a through-hole for a grounding and a through-hole for a power supply disposed adjacent to each other, and a build-up layer formed on one surface of the core substrate. The through-hole for a grounding and the through-hole for a power supply have a cross-sectional shape perpendicular to a thickness direction of the core substrate, being any one of a triangular shape, a quadrangular shape and a hexagonal shape, containing a corner portion and a side portion connecting between the corner portions. The side portions of the through-hole for a grounding and the through-hole for a power supply being mutually adjacent are disposed so as to face each other.
    Type: Application
    Filed: April 20, 2015
    Publication date: October 22, 2015
    Applicant: KYOCERA Circuit Solutions, Inc.
    Inventors: Makoto SHIROSHITA, Hisayoshi WADA
  • Publication number: 20150000965
    Abstract: A wiring board 10a according to the present invention is provided with an insulating board 1 laminated at least one insulating layer 1b having a via hole 8 on at least one surface of a core layer 1a, a via conductor 2b formed inside the via hole 8 and containing a low resistance material, and a connection pad formed at the surface of the insulating layer 1b and including a thin film resistor layer 3a containing a high resistance material, wherein the thin film resistor layer 3a is adhered to the insulating layer 1b in such a manner as to cover the via conductor 2b and the insulating layer 1b surrounding the via conductor 2b.
    Type: Application
    Filed: June 27, 2014
    Publication date: January 1, 2015
    Applicant: KYOCERA SLC TECHNOLOGIES CORPORATION
    Inventor: Makoto SHIROSHITA