Patents by Inventor Makoto Suwa
Makoto Suwa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10603332Abstract: A method to suppress obesity, comprising administering to a subject in need thereof an effective amount of a composition comprising the following components (A) and (B): (A) oleuropein; and (B) a sulforaphane compound, wherein the amount of component (A) alone contained in the composition does not result in a fat accumulation-suppressing effect, and the amount of component (B) alone contained in the composition does not result in a fat accumulation-suppressing effect.Type: GrantFiled: May 26, 2017Date of Patent: March 31, 2020Assignee: SUNSTAR INC.Inventors: Youko Sono, Makoto Suwa, Motonobu Matsumoto
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Publication number: 20170258822Abstract: An object of the present invention is to provide an obesity-suppressing composition that suppresses fat accumulation in adipocytes and that has an effect of suppressing body weight gain. The present invention provides an obesity-suppressing composition comprising the following components (A) and (B): (A) at least one member selected from the group consisting of oleuropein and hydroxytyrosol; (B) at least one member selected from the group consisting of sulforaphane compounds and willow extract.Type: ApplicationFiled: May 26, 2017Publication date: September 14, 2017Applicant: SUNSTAR INC.Inventors: Youko SONO, Makoto SUWA, Motonobu MATSUMOTO
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Publication number: 20160206643Abstract: An object of the present invention is to provide an obesity-suppressing composition that suppresses fat accumulation in adipocytes and that has an effect of suppressing body weight gain. The present invention provides an obesity-suppressing composition comprising the following components (A) and (B): (A) at least one member selected from the group consisting of oleuropein and hydroxytyrosol; (B) at least one member selected from the group consisting of sulforaphane compounds and willow extract.Type: ApplicationFiled: September 29, 2014Publication date: July 21, 2016Applicant: SUNSTAR INC.Inventors: Youko SONO, Makoto SUWA, Motonobu MATSUMOTO
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Patent number: 6954103Abstract: A manner of generating internal voltages such as a high voltage, an intermediate voltage and an internal power supply voltage is switched in accordance with a power supply level setting signal. When the voltage level of an external power supply voltage is low, a current drive transistor receiving an output of a comparing circuit and an auxiliary drive transistor are forcedly set in a conductive state, and external power supply voltage is transmitted on an internal power supply line. At this time, the comparing operation of the comparing circuit is stopped. When the level of the external power supply voltage is high, the comparing circuit is activated down convert the external power supply voltage for generating a peripheral power supply voltage on the internal power supply line.Type: GrantFiled: May 2, 2003Date of Patent: October 11, 2005Assignee: Renesas Technology Corp.Inventors: Tadaaki Yamauchi, Junko Matsumoto, Takeo Okamoto, Makoto Suwa, Tetsuichiro Ichiguchi, Hideki Yonetani, Tsutomu Nagasawa, Zengcheng Tian
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Patent number: 6873563Abstract: Data pad regions are arranged in four divided regions of a semiconductor memory chip of a rectangular shape, respectively, and data pads are selectively utilized in each of the four divided regions in accordance with a word structure. Thus, it is possible to implement a semiconductor memory chip capable of being assembled in both a single chip package and a multi chip package.Type: GrantFiled: March 19, 2003Date of Patent: March 29, 2005Assignee: Renesas Technology Corp.Inventors: Makoto Suwa, Junko Matsumoto, Tadaaki Yamauchi, Takeo Okamoto, Tetsuichiro Ichiguchi, Hideki Yonetani, Tsutomu Nagasawa, Zengcheng Tian
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Patent number: 6833148Abstract: The green vegetable puree production process according to the present invention, which contains a grinding step and an acid addition step and does not include a heating step, produces an unheated green vegetable puree having no catalase activity, containing an acid or acids and having a pH of 2.7 to 4.1. The puree sufficiently maintains the original flavor and taste and freshness of vegetables and is suitable for use in the preparation of foods, especially for vegetable juices.Type: GrantFiled: April 16, 2001Date of Patent: December 21, 2004Assignee: Sunstar Inc.Inventors: Keiko Yamamoto, Makoto Suwa
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Patent number: 6813210Abstract: The semiconductor memory device includes a refresh timer for determining a refresh cycle of self-refresh operation. The refresh timer includes a voltage regulator, a ring oscillator and a counter. The voltage regulator generates a bias voltage having positive temperature characteristics. The ring oscillator varies an oscillation cycle of a pulse signal according to the bias voltage. The counter counts a prescribed number of pulse signals and generates a refresh signal for executing refresh operation. The semiconductor memory device thus varies the refresh cycle according to a temperature change, and executes refresh operation with an appropriate refresh cycle.Type: GrantFiled: November 21, 2002Date of Patent: November 2, 2004Assignee: Renesas Technology Corp.Inventors: Takeo Okamoto, Tetsuichiro Ichiguchi, Hideki Yonetani, Tsutomu Nagasawa, Tadaaki Yamauchi, Makoto Suwa, Junko Matsumoto, Zengcheng Tian
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Patent number: 6784718Abstract: An input circuit includes a gate circuit receiving an output power supply voltage that determines the logic level of an input signal or a comparison circuit receiving an input signal and a reference voltage depending on the output power supply voltage supplied from a pad different from a power supply pad for an output circuit.Type: GrantFiled: August 30, 2002Date of Patent: August 31, 2004Assignee: Renesas Technology Corp.Inventors: Takeo Okamoto, Tadaaki Yamauchi, Shinichi Jinbo, Makoto Suwa, Junko Matsumoto
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Patent number: 6775177Abstract: A row address decoder of a semiconductor memory device generates internal row address signals RAD<0:11> and /RAD<0:11> by switching most significant bit and least significant bit of row address signals RA<0:11> and /RA<0:11> that correspond to address signals A0 to A11, respectively. In a twin cell mode, the least significant bits RAD<0> and /RAD<0> of the internal row address signals corresponding to the most significant bits RA<11> and /RA<11> of the row address signal that are not used are selected simultaneously by row address decoder, and two adjacent word lines are activated simultaneously. Consequently, the configuration of memory cell in the semiconductor memory device can electrically be switched from the normal single memory cell type to the twin memory cell type.Type: GrantFiled: November 19, 2002Date of Patent: August 10, 2004Assignee: Renesas Technology Corp.Inventors: Takeo Okamoto, Tetsuichiro Ichiguchi, Hideki Yonetani, Tsutomu Nagasawa, Makoto Suwa, Zengcheng Tian, Tadaaki Yamauchi, Junko Matsumoto
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Patent number: 6724679Abstract: A semiconductor memory device includes banks, predecoders, a latch circuit, a counter, a fuse and buffers. The bank includes a plurality of memory cells arranged in rows and columns, and others. The predecoders are disposed in a central portion of the semiconductor memory device. The predecoder produces a predecode signal for selecting each of the banks based on a bank address received from the buffer, and outputs the predecode signal to the banks. The predecoder produces the predecode signal for selecting each of the banks based on the bank address, and outputs the predecode signal to the banks. Consequently, interconnections in the central portion can be reduced in number.Type: GrantFiled: April 22, 2002Date of Patent: April 20, 2004Assignee: Renesas Technology Corp.Inventors: Tsutomu Nagasawa, Hideki Yonetani, Kozo Ishida, Shinichi Jinbo, Makoto Suwa, Tadaaki Yamauchi, Junko Matsumoto, Zengcheng Tian, Takeo Okamoto
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Patent number: 6724223Abstract: A clock buffer of a DRAM includes: a first NAND gate which is driven by a first internal power supply voltage (2.5 V) and which determines the level of an input clock signal if the DRAM is used for a TTL-system interface (MLV=2.5 V); and a second NAND gate which is driven by a second internal power supply voltage (1.8 V) and which determines the level of the input clock signal if the DRAM is used for a 1.8 V-system interface (MLV=0 V). Accordingly, in each of the first and second NAND gates, sizes of four MOS transistors can be set at optimum values, respectively.Type: GrantFiled: November 5, 2002Date of Patent: April 20, 2004Assignee: Renesas Technology Corp.Inventors: Tetsuichiro Ichiguchi, Tsutomu Nagasawa, Tadaaki Yamauchi, Zengcheng Tian, Makoto Suwa, Junko Matsumoto, Takeo Okamoto, Hideki Yonetani
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Publication number: 20030218931Abstract: The semiconductor memory device includes a refresh timer for determining a refresh cycle of self-refresh operation. The refresh timer includes a voltage regulator, a ring oscillator and a counter. The voltage regulator generates a bias voltage having positive temperature characteristics. The ring oscillator varies an oscillation cycle of a pulse signal according to the bias voltage. The counter counts a prescribed number of pulse signals and generates a refresh signal for executing refresh operation. The semiconductor memory device thus varies the refresh cycle according to a temperature change, and executes refresh operation with an appropriate refresh cycle.Type: ApplicationFiled: November 21, 2002Publication date: November 27, 2003Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Takeo Okamoto, Tetsuichiro Ichiguchi, Hideki Yonetani, Tsutomu Nagasawa, Tadaaki Yamauchi, Makoto Suwa, Junko Matsumoto, Zengcheng Tian
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Publication number: 20030214344Abstract: Data pad regions are arranged in four divided regions of a semiconductor memory chip of a rectangular shape, respectively, and data pads are selectively utilized in each of the four divided regions in accordance with a word structure. Thus, it is possible to implement a semiconductor memory chip capable of being assembled in both a single chip package and a multi chip package.Type: ApplicationFiled: March 19, 2003Publication date: November 20, 2003Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Makoto Suwa, Junko Matsumoto, Tadaaki Yamauchi, Takeo Okamoto, Tetsuichiro Ichiguchi, Hideki Yonetani, Tsutomu Nagasawa, Zengcheng Tian
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Publication number: 20030214832Abstract: A row address decoder of a semiconductor memory device generates internal row address signals RAD<0:11>and /RAD<0:11>by switching most significant bit and least significant bit of row address signals RA<0:11>and /RA<0:11>that correspond to address signals A0 to A11, respectively. In a twin cell mode, the least significant bits RAD<0>and /RAD<0>of the internal row address signals corresponding to the most significant bits RA<11>and /RA<11>of the row address signal that are not used are selected simultaneously by row address decoder, and two adjacent wold lines are activated simultaneously. Consequently, the configuration of memory cell in the semiconductor memory device can electrically be switched from the normal single memory cell type to the twin memory cell type.Type: ApplicationFiled: November 19, 2002Publication date: November 20, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Takeo Okamoto, Tetsuichiro Ichiguchi, Hideki Yonetani, Tsutomu Nagasawa, Makoto Suwa, Zengcheng Tian, Tadaaki Yamauchi, Junko Matsumoto
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Publication number: 20030213972Abstract: A clock buffer of a DRAM includes: a first NAND gate which is driven by a first internal power supply voltage (2.5 V) and which determines the level of an input clock signal if the DRAM is used for a TTL-system interface (MLV=2.5 V); and a second NAND gate which is driven by a second internal power supply voltage (1.8 V) and which determines the level of the input clock signal if the DRAM is used for a 1.8 V-system interface (MLV=0 V). Accordingly, in each of the first and second NAND gates, sizes of four MOS transistors can be set at optimum values, respectively.Type: ApplicationFiled: November 5, 2002Publication date: November 20, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Tetsuichiro Ichiguchi, Tsutomu Nagasawa, Tadaaki Yamauchi, Zengcheng Tian, Makoto Suwa, Junko Matsumoto, Takeo Okamoto, Hideki Yonetani
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Publication number: 20030214345Abstract: A manner of generating internal voltages such as a high voltage, an intermediate voltage and an internal power supply voltage is switched in accordance with a power supply level setting signal. When the voltage level of an external power supply voltage is low, a current drive transistor receiving an output of a comparing circuit and an auxiliary drive transistor are forcedly set in a conductive state, and external power supply voltage is transmitted on an internal power supply line. At this time, the comparing operation of the comparing circuit is stopped. When the level of the external power supply voltage is high, the comparing circuit is activated down convert the external power supply voltage for generating a peripheral power supply voltage on the internal power supply line.Type: ApplicationFiled: May 2, 2003Publication date: November 20, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Tadaaki Yamauchi, Junko Matsumoto, Takeo Okamoto, Makoto Suwa, Tetsuichiro Ichiguchi, Hideki Yonetani, Tsutomu Nagasawa, Zengcheng Tian
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Patent number: 6625050Abstract: Pad lines are placed on the peripheral region of a chip along EAST band and WEST band (E/W band). In order to allow the chip with pads arranged on the peripheral region to be adaptable to a TSOP, VDD and VSS pads are arranged on the edge region on NORTH band and SOUTH band (N/S band) near the center of the N/S band. Moreover, in consideration of frame design for the TSOP, some pads on the ends of the pad lines among the pads included in the pad lines are arranged in reverse order relative to the order of pins. Further, VDDQ and VSSQ pads are arranged in the same order as that of pins for a package which requires no consideration of frame design. On the other hand, for use in a BGA package, VDD and VSS pads are arranged in pairs at respective ends of the pad lines. A semiconductor memory device with this pad arrangement is accordingly adaptable to various types of packages.Type: GrantFiled: May 14, 2002Date of Patent: September 23, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Makoto Suwa, Shinichi Jinbo, Zengcheng Tian, Takeo Okamoto, Kozo Ishida, Hideki Yonetani, Tsutomu Nagasawa, Tadaaki Yamauchi, Junko Matsumoto
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Publication number: 20030081443Abstract: Pad lines are placed on the peripheral region of a chip along EAST band and WEST band (E/W band). In order to allow the chip with pads arranged on the peripheral region to be adaptable to a TSOP, VDD and VSS pads are arranged on the edge region on NORTH band and SOUTH band (N/S band) near the center of the N/S band. Moreover, in consideration of frame design for the TSOP, some pads on the ends of the pad lines among the pads included in the pad lines are arranged in reverse order relative to the order of pins. Further, VDDQ and VSSQ pads are arranged in the same order as that of pins for a package which requires no consideration of frame design. On the other hand, for use in a BGA package, VDD and VSS pads are arranged in pairs at respective ends of the pad lines. A semiconductor memory device with this pad arrangement is accordingly adaptable to various types of packages.Type: ApplicationFiled: May 14, 2002Publication date: May 1, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Makoto Suwa, Shinichi Jinbo, Zengcheng Tian, Takeo Okamoto, Kozo Ishida, Hideki Yonetani, Tsutomu Nagasawa, Tadaaki Yamauchi, Junko Matsumoto
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Publication number: 20030080795Abstract: An input circuit is comprised of a gate circuit receiving an output power supply voltage that determines the logic level of an input signal or a comparison circuit receiving an input signal and a reference voltage depending on the output power supply voltage supplied from a pad different from a power supply pad for an output circuit. Even if the output power supply voltage varies to cause the input signal to change, whether the input signal is at H level or L level can accurately be determined and an internal signal is generated correctly.Type: ApplicationFiled: August 30, 2002Publication date: May 1, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Takeo Okamoto, Tadaaki Yamauchi, Shinichi Jinbo, Makoto Suwa, Junko Matsumoto
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Publication number: 20030081490Abstract: A semiconductor memory device includes banks, predecoders, a latch circuit, a counter, a fuse and buffers. The bank includes a plurality of memory cells arranged in rows and columns, and others. The predecoders are disposed in a central portion of the semiconductor memory device. The predecoder produces a predecode signal for selecting each of the banks based on a bank address received from the buffer, and outputs the predecode signal to the banks. The predecoder produces the predecode signal for selecting each of the banks based on the bank address, and outputs the predecode signal to the banks. Consequently, interconnections in the central portion can be reduced in number.Type: ApplicationFiled: April 22, 2002Publication date: May 1, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Tsutomu Nagasawa, Hideki Yonetani, Kozo Ishida, Shinichi Jinbo, Makoto Suwa, Tadaaki Yamauchi, Junko Matsumoto, Zengcheng Tian, Takeo Okamoto