Patents by Inventor Makoto Suwada
Makoto Suwada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10354715Abstract: A semiconductor device in which a plurality of chips each including a memory circuit is stacked, the semiconductor device includes a transmission path including a plurality of microbumps formed in the plurality of chips, measurement circuitry that detects a reflected waveform when a signal is transmitted in the transmission path and measures propagation delay time for a certain part on the transmission path from the reflected waveform that has been detected, determination circuitry that calculates temperature of each memory area that corresponds to the certain part from the propagation delay time that has been measured by the measurement circuitry, and control circuitry that sets a refresh interval of each memory area, based on the temperature of each memory area, which has been calculated by the determination circuitry, and executes a refresh operation of the memory circuit in each memory area at the refresh interval that has been set.Type: GrantFiled: November 27, 2017Date of Patent: July 16, 2019Assignee: FUJITSU LIMITEDInventor: Makoto Suwada
-
Patent number: 10224078Abstract: A semiconductor device in which a plurality of chips each including a memory circuit are stacked, the semiconductor device includes measurement circuitry each of which is disposed in each of a plurality of memory areas of the plurality of chips and each of which measures a temperature, calculation circuitry that calculates a temperature of each of the memory areas based on the temperature measured by the measurement circuitry and a temperature obtained from a thermal resistance model of the semiconductor device, and control circuitry that sets a refresh interval of each of the memory areas based on the temperature of each of the memory areas, which has been calculated by the calculation circuitry, and performs a refresh operation of the memory circuit of each of the memory areas at the set refresh interval.Type: GrantFiled: October 25, 2017Date of Patent: March 5, 2019Assignee: FUJITSU LIMITEDInventors: Yoshitsugu Goto, Makoto Suwada
-
Publication number: 20180166124Abstract: A semiconductor device in which a plurality of chips each including a memory circuit is stacked, the semiconductor device includes a transmission path including a plurality of microbumps formed in the plurality of chips, measurement circuitry that detects a reflected waveform when a signal is transmitted in the transmission path and measures propagation delay time for a certain part on the transmission path from the reflected waveform that has been detected, determination circuitry that calculates temperature of each memory area that corresponds to the certain part from the propagation delay time that has been measured by the measurement circuitry, and control circuitry that sets a refresh interval of each memory area, based on the temperature of each memory area, which has been calculated by the determination circuitry, and executes a refresh operation of the memory circuit in each memory area at the refresh interval that has been set.Type: ApplicationFiled: November 27, 2017Publication date: June 14, 2018Applicant: FUJITSU LIMITEDInventor: MAKOTO SUWADA
-
Publication number: 20180166123Abstract: A semiconductor device in which a plurality of chips each including a memory circuit are stacked, the semiconductor device includes measurement circuitry each of which is disposed in each of a plurality of memory areas of the plurality of chips and each of which measures a temperature, calculation circuitry that calculates a temperature of each of the memory areas based on the temperature measured by the measurement circuitry and a temperature obtained from a thermal resistance model of the semiconductor device, and control circuitry that sets a refresh interval of each of the memory areas based on the temperature of each of the memory areas, which has been calculated by the calculation circuitry, and performs a refresh operation of the memory circuit of each of the memory areas at the set refresh interval.Type: ApplicationFiled: October 25, 2017Publication date: June 14, 2018Applicant: FUJITSU LIMITEDInventors: Yoshitsugu Goto, MAKOTO SUWADA
-
Patent number: 9653380Abstract: A substrate is disclosed, which can remove heat from a stacked body of semiconductor elements through a phase change of a coolant. The substrate of the application includes: a stacked body of semiconductor elements; a first channel forming a path, receiving circulation of a first coolant, in a surface of the stacked body; and a second channel forming a path, receiving circulation of a second coolant having a boiling point higher than the boiling point of the first coolant, in an inter-layer portion of the stacked body.Type: GrantFiled: April 26, 2016Date of Patent: May 16, 2017Assignee: FUJITSU LIMITEDInventors: Makoto Suwada, Mitsutaka Yamada, Masumi Suzuki, Michimasa Aoki, Keizou Takemura, Shinichirou Okamoto, Kenji Katsumata, Jie Wei
-
Patent number: 9563221Abstract: A semiconductor device includes a substrate; a first through-electrode penetrating the substrate and connected to a power source or a reference potential point; a second through-electrode penetrating the substrate; a power section connected between the substrate and the second through-electrode and configured to output a DC voltage between the substrate and the second through-electrode; a voltage control section configured to control the DC voltage to be output by the power section; and a measurement section connected to the first through-electrode and configured to measure a power impedance of the first through-electrode, wherein the voltage control section is configured to control a value of the DC voltage output by the power section, such that the power impedance of the first through-electrode measured by the measurement section is equal to or less than a predetermined value within a predetermined frequency range including a frequency of noise occurring in the first through-electrode.Type: GrantFiled: March 3, 2016Date of Patent: February 7, 2017Assignee: FUJITSU LIMITEDInventor: Makoto Suwada
-
Patent number: 9515005Abstract: A package mounting structure includes: a first substrate having wiring; a second substrate having wiring; at least one cooling unit having a first face and a second face different from the first face; at least one power supply unit that is mounted on the first substrate and is joined to the first face of the cooling unit; and at least one electronic component that is mounted on the second substrate and is joined to the second face of the cooling unit, wherein the power supply unit supplies power to the electronic component through the wiring of the first substrate, the cooling unit, and the wiring of the second substrate.Type: GrantFiled: May 5, 2014Date of Patent: December 6, 2016Assignee: FUJITSU LIMITEDInventors: Shunji Baba, Masateru Koide, Manabu Watanabe, Takashi Kanda, Kenji Fukuzono, Yuki Hoshino, Makoto Suwada
-
Publication number: 20160351471Abstract: A substrate is disclosed, which can remove heat from a stacked body of semiconductor elements through a phase change of a coolant. The substrate of the application includes: a stacked body of semiconductor elements; a first channel forming a path, receiving circulation of a first coolant, in a surface of the stacked body; and a second channel forming a path, receiving circulation of a second coolant having a boiling point higher than the boiling point of the first coolant, in an inter-layer portion of the stacked body.Type: ApplicationFiled: April 26, 2016Publication date: December 1, 2016Applicant: FUJITSU LIMITEDInventors: MAKOTO SUWADA, Mitsutaka YAMADA, Masumi SUZUKI, Michimasa AOKI, Keizou Takemura, Shinichirou OKAMOTO, Kenji Katsumata, JIE WEI
-
Patent number: 9508705Abstract: An electronic part includes: a substrate; a first electrode configured to extend through the substrate and have a first opening size; a second electrode configured to extend through the substrate and have a second opening size; a switching section configured to switch between connection of the first electrode to a first power line and connection of the second electrode to the first power line; and a third electrode configured to extend through the substrate and be connected to a second power line different in potential from the first power line, a capacitance between the first and third electrodes and a capacitance between the second and third electrodes being different.Type: GrantFiled: March 30, 2016Date of Patent: November 29, 2016Assignee: FUJITSU LIMITEDInventor: Makoto Suwada
-
Patent number: 9478522Abstract: An electronic part includes: a substrate; a first electrode configured to extend through the substrate and have a first opening size; a second electrode configured to extend through the substrate and have a second opening size; a switching section configured to switch between connection of the first electrode to a first power line and connection of the second electrode to the first power line; and a third electrode configured to extend through the substrate and be connected to a second power line different in potential from the first power line, a capacitance between the first and third electrodes and a capacitance between the second and third electrodes being different.Type: GrantFiled: June 29, 2015Date of Patent: October 25, 2016Assignee: FUJITSU LIMITEDInventor: Makoto Suwada
-
Publication number: 20160291628Abstract: A semiconductor device includes a substrate; a first through-electrode penetrating the substrate and connected to a power source or a reference potential point; a second through-electrode penetrating the substrate; a power section connected between the substrate and the second through-electrode and configured to output a DC voltage between the substrate and the second through-electrode; a voltage control section configured to control the DC voltage to be output by the power section; and a measurement section connected to the first through-electrode and configured to measure a power impedance of the first through-electrode, wherein the voltage control section is configured to control a value of the DC voltage output by the power section, such that the power impedance of the first through-electrode measured by the measurement section is equal to or less than a predetermined value within a predetermined frequency range including a frequency of noise occurring in the first through-electrode.Type: ApplicationFiled: March 3, 2016Publication date: October 6, 2016Applicant: FUJITSU LIMITEDInventor: MAKOTO SUWADA
-
Publication number: 20160211249Abstract: An electronic part includes: a substrate; a first electrode configured to extend through the substrate and have a first opening size; a second electrode configured to extend through the substrate and have a second opening size; a switching section configured to switch between connection of the first electrode to a first power line and connection of the second electrode to the first power line; and a third electrode configured to extend through the substrate and be connected to a second power line different in potential from the first power line, a capacitance between the first and third electrodes and a capacitance between the second and third electrodes being different.Type: ApplicationFiled: March 30, 2016Publication date: July 21, 2016Applicant: FUJITSU LIMITEDInventor: MAKOTO SUWADA
-
Publication number: 20160211243Abstract: A laminated chip includes: a first chip; a first wiring layer formed on the first chip; a second chip; a second wiring layer formed on the second chip; and a layer disposed between the first wiring layer and the second wiring layer, the layer includes an adhesive agent configured to bond the first wiring layer and the second wiring layer; a plurality of first bumps connected to the first wiring layer; a plurality of second bumps connected to the second wiring layer; and solder connected to the plurality of first bumps and the plurality of second bumps.Type: ApplicationFiled: December 15, 2015Publication date: July 21, 2016Applicant: FUJITSU LIMITEDInventors: MAKOTO SUWADA, Shunji Baba, TAKASHI KANDA, NORIO KAINUMA
-
Patent number: 9331752Abstract: A memory includes a control layer that includes a first radio communication unit that performs radio communication and a control unit that controls the radio communication; and a memory layer that includes a second radio communication unit that performs the radio communication with the first radio communication unit and a first storage unit that stores information, the memory layer being provided on the control layer.Type: GrantFiled: July 10, 2014Date of Patent: May 3, 2016Assignee: FUJITSU LIMITEDInventors: Daisuke Usui, Makoto Suwada
-
Publication number: 20160020268Abstract: An electronic part includes: a substrate; a first electrode configured to extend through the substrate and have a first opening size; a second electrode configured to extend through the substrate and have a second opening size; a switching section configured to switch between connection of the first electrode to a first power line and connection of the second electrode to the first power line; and a third electrode configured to extend through the substrate and be connected to a second power line different in potential from the first power line, a capacitance between the first and third electrodes and a capacitance between the second and third electrodes being different.Type: ApplicationFiled: June 29, 2015Publication date: January 21, 2016Inventor: MAKOTO SUWADA
-
Patent number: 9230964Abstract: A semiconductor device includes: a first semiconductor chip having a first antenna that is formed in a first hole provided in the first semiconductor chip, has an inclined surface inclined with respect to a central line of the first hole, and transmits and receives a radio wave; and a second semiconductor chip stacked over the first semiconductor chip, the second semiconductor chip having a second antenna that is formed in a second hole provided in the second semiconductor chip, has an inclined surface inclined with respect to a central line of the second hole, and transmits and receives a radio wave, wherein the first antenna and the second antenna are disposed so that the inclined surface of the first antenna and the inclined surface of the second antenna face each other.Type: GrantFiled: November 13, 2014Date of Patent: January 5, 2016Assignee: FUJITSU LIMITEDInventors: Naoaki Nakamura, Makoto Suwada
-
Publication number: 20150162276Abstract: A semiconductor device includes: a first semiconductor chip having a first antenna that is formed in a first hole provided in the first semiconductor chip, has an inclined surface inclined with respect to a central line of the first hole, and transmits and receives a radio wave; and a second semiconductor chip stacked over the first semiconductor chip, the second semiconductor chip having a second antenna that is formed in a second hole provided in the second semiconductor chip, has an inclined surface inclined with respect to a central line of the second hole, and transmits and receives a radio wave, wherein the first antenna and the second antenna are disposed so that the inclined surface of the first antenna and the inclined surface of the second antenna face each other.Type: ApplicationFiled: November 13, 2014Publication date: June 11, 2015Inventors: Naoaki NAKAMURA, Makoto SUWADA
-
Publication number: 20150087229Abstract: A memory includes a control layer that includes a first radio communication unit that performs radio communication and a control unit that controls the radio communication; and a memory layer that includes a second radio communication unit that performs the radio communication with the first radio communication unit and a first storage unit that stores information, the memory layer being provided on the control layer.Type: ApplicationFiled: July 10, 2014Publication date: March 26, 2015Applicant: FUJITSU LIMITEDInventors: Daisuke USUI, MAKOTO SUWADA
-
Publication number: 20140376187Abstract: A package mounting structure includes: a first substrate having wiring; a second substrate having wiring; at least one cooling unit having a first face and a second face different from the first face; at least one power supply unit that is mounted on the first substrate and is joined to the first face of the cooling unit; and at least one electronic component that is mounted on the second substrate and is joined to the second face of the cooling unit, wherein the power supply unit supplies power to the electronic component through the wiring of the first substrate, the cooling unit, and the wiring of the second substrate.Type: ApplicationFiled: May 5, 2014Publication date: December 25, 2014Applicant: FUJITSU LIMITEDInventors: Shunji Baba, Masateru Koide, Manabu Watanabe, Takashi Kanda, Kenji Fukuzono, Yuki Hoshino, Makoto Suwada
-
Patent number: 8756553Abstract: A design support apparatus acquires position information for a signal wire that is to be disposed in wiring layer stacked on an insulation layer. Subsequently, the design support apparatus acquires position information for an area obtained by projecting, in a direction for glass fiber bundles to be stacked on one another, the glass fiber bundles in an insulation layer actually used. The design support apparatus converts the position information for the signal wire that is to be disposed into position information for a position in the area of the glass fiber bundles such that the signal wire is included in the area of the glass fiber bundles in the insulation layer actually used. The design support apparatus outputs the converted position information.Type: GrantFiled: December 23, 2012Date of Patent: June 17, 2014Assignee: Fujitsu LimitedInventor: Makoto Suwada